Tracy Chea joined Silicon Labs in May 2018 as an IT Support intern working under Randy Ferguson, the service delivery manager. As an intern, her responsibilities include providing technological support for employees, managing the Windows 7-to-Windows 10-migration process, and creating websites and documentation to improve service desk efficiency. She attends the University of Texas at Austin where she’s pursuing a bachelor’s degree in MIS and a certificate in computer science.

On a typical day, Tracy arrives at the office at 8am and starts her day with a granola bar from the company’s microkitchen and an IT team meeting, where the group shares updates on new deployments and urgent problems needed to be solved. Every week, she also has a service desk meeting where Randy, her manager, reviews weekly tasks and everyone shares what they have been working on.

Tracy is spending her summer working on several projects, including building websites, imaging laptops, and learning PowerShell. Her work schedule is very flexible and she has the freedom to switch between projects easily. In her free time, she also helps solve IT ticket requests. 

Every other week, Tracy's team bonds over a team lunch. This week’s lunch was at Casino el Camino, which is within walking distance from the office, and it quickly became one of her favorite burger restaurants. After lunch she spotted Everett, the Chief Information Officer, making his way back to the corporate office on a Lime-a popular electric scooter sharing service in Austin.

Following lunch, Tracy continues to work on her projects. Her favorite thing about Silicon Labs is being able to play with all the technology and getting the chance to fix things- especially the laptops of fellow interns!

Several days a month, there are intern events hosted by the People Team, which is the company’s HR team. So far, out of the stand-up comedy show, company pool party, lunch-and-learns, and volunteering events, Tracy enjoyed the service event with Habitat for Humanity the most.

“I really enjoy philanthropy, and it’s cool to intern for a company that also is committed to serving the community. A few hours out of a day may leave a lasting impact, and that impact may encourage those people to help someone else. It's like a chain reaction.”

At the end of the day, Tracy reflects upon her experiences in a journal. She finds it helpful to record the things she has learned. Before she heads for the parking garage at the end of the day, she makes one final check of her emails and IT tickets to make sure everything is clear before she leaves.

Overall, Tracy’s favorite part about Silicon Labs has been the exposure to new things. "Since I like working hands-on with equipment, it was really cool when I got the chance to see my coworker’s projects on audio and visual settings in the conference rooms. Silicon Labs has provided me a lot of exploration, and I like being able to experience a bit of everything.”

Barbara Baylor joined Silicon Labs in 2006 as the distribution coordinator in Austin. This role gives her the opportunity to interact with virtually every department and has allowed her to interact and form relationships with Silicon Labs employees around the world. Barbara says she looks forward to coming to work every day, “because you never know who you will meet or what you will learn.” On a typical work day, her responsibilities include monitoring printers on all floors, making bindings for training manuals, and wrapping, shipping, and receiving packages. “I enjoy helping people and I want to help everyone to be successful.”

Being a native of Germany, Barbara enjoys working at a company that is multicultural and one that believes in hiring, fostering, and empowering great talent. “I like that you are not just a number. You are a person with a name and a story.” Because she has worked here for 12 years, she’s heard many stories and connected people from the same home countries or with similar interests and hobbies. She has also received hundreds of post cards from Silicon Labs employees traveling across the world. These postcards cover three bulletin boards and serve as a reminder of the relationships she’s built here.  “It’s nice to receive post cards from the beautiful places people travel and have that connection with them.”

Prior to joining the Silicon Labs team, she spent 25 years at the Deutsche Post, a German postal service. When asked if she could travel to any country, Barbara expressed wanting to return to Germany. It has been 10 years since she last visited her home country, and she “looks forward to seeing her family and friends” in October.

We are thankful to have someone so generous and dedicated on the Silicon Labs team. Thank you, Barbara, for keeping us all connected and helping us be successful!

Hi all,

I'm pleased to announce the latest SDK that includes improvements and bug fixes for our Bluetooth, Thread, Zigbee, and MCU product families. This release provides the following: 

• EmberZNet 6.3.0 (Full release here)
  • Zigbee Pro 2017 (R22) compliant stack w/ GPPB and SE1.4/GBCS support
  • Dynamic block request delay support for OTA upgrades
  • Sub-GHz only mode support for SE1.4/GBCS
  • NVM3 G.A integration
  • Gecko Bootloader LZMA decompression support
  • IAR EWARM 7.80.4 and GCC 7.2.1 support
• Silicon Labs - Thread 2.7.0 (Full release here)
  • Thread with Micrium OS Beta support 
  • DotDot DTLS security support
  • DotDot resource directory and discovery support
  • DotDot conformance testing support
  • IAR EWARM 7.8.4 and GCC 7.2.1 support
  • GRL Test Harness support bug fixes
• Flex SDK (Full release here)
  • Version 2.2.1.0 GA – enhanced support for QFN68 variants of EFR32xG12
  • Version 2.2.2.0 GA – RAIL and Connect feature enhancements and bug fixes
  • Version 2.2.2.1 GA – minor metadata changes, no application or stack changes
• Bluetooth SDK (Full release here)
  • +20dBm support and AFH
  • Long advertisement packets & additional RF channels 
  • Bluetooth + RAIL DMP enhancements 
  • BGM13P32 support
• MCU (Full release here)
  • Gecko LE-USB support on GG11, to complement existing Micrium USB 
  • Micrium OpenCAN support for GG11/TG11

Need help? Please contact Silicon Labs Technical Support.

~Tabi

One of our timing customers sees a real opportunity in the way FPGA-based designs are commercialized and brought to market.

Jim Bittman, principal hardware engineer, founded BittWare in 1989. The company was recently acquired and today is BittWare, a Molex company, with headquarters in Concord, New Hampshire. Back in the 1990s, BittWare was focused on DSP boards—but in the early 2000s the company realized a new opportunity for growth using a new generation of powerful FPGAs. Switching from designing and manufacturing DSP-based boards to those with large FPGAs was not simple, however, as the nature of these devices brought significant engineering challenges for early adopters like BittWare.

FPGAs combine programmable logic, embedded high-speed transceivers, protocol IP controllers, digital signal processing, memory controllers, and a tremendous amount of computational power. FPGAs are truly the brains in modern electronic designs. But to unlock and harness the power of the industry’s latest FPGAs, system designers are faced with a formidable system integration challenge. Designs require network connectivity, high speed serial interfaces to share data across chips and boards, memory, power, timing and other resources. Designers need to develop solutions that can be brought to market quickly and efficiently. And there is also a need to develop customized solutions that are uniquely tailored for different markets and customers.

That’s where BittWare comes in. BittWare develops Intel and Xilinx board-level solutions that combine FPGAs with 10/40/100GbE high-speed networking interfaces, PCIe Gen 1, Gen 2 or Gen 3 connectivity, DDR4 memory, Silicon Labs low jitter programmable clocks and a board management controller for advanced system monitoring. The boards are based upon industry-standard commercially-off-the-shelf (COTS) form factors to ensure compatibility and interoperability with chassis and single board computer vendors. The benefit? BittWare’s customers get a turnkey solution that significantly reduces technology risk and accelerates time-to-revenue.

Another challenge is that different applications often require different frequency clocks to support different networking protocols and control plane functions. BittWare and Silicon Labs worked closely together to address this challenge by building support into BittWare’s software so that their customers can directly customize Silicon Labs’ programmable clocks for their own applications. One common hardware platform can be easily adapted to support a broad range of different applications. The hardware, including clocking, is remotely field-upgradable, so new applications can be enabled quickly via software upgrades.

A broad range of markets are benefiting from these system-level turnkey solutions, including broadcast video, finance, instrumentation, government and military/aerospace. In particular, applications like cyber security, high frequency trading, and high-performance computing in data centers require rapid reprogrammability to support innovative new features and services.

By combining Intel and Xilinx programmable FPGAs and Silicon Labs programmable clocks in their designs, BittWare is powering the next wave of innovation in high-speed electronics design.

To learn more about Silicon Labs' timing solutions, click here. 

One of our timing customers sees a real opportunity in the way FPGA-based designs are commercialized and brought to market.

Jim Bittman, principal hardware engineer, founded BittWare in 1989. The company was recently acquired and today is BittWare, a Molex company, with headquarters in Concord, New Hampshire. Back in the 1990s, BittWare was focused on DSP boards—but in the early 2000s the company realized a new opportunity for growth using a new generation of powerful FPGAs. Switching from designing and manufacturing DSP-based boards to those with large FPGAs was not simple, however, as the nature of these devices brought significant engineering challenges for early adopters like BittWare.

FPGAs combine programmable logic, embedded high-speed transceivers, protocol IP controllers, digital signal processing, memory controllers, and a tremendous amount of computational power. FPGAs are truly the brains in modern electronic designs. But to unlock and harness the power of the industry’s latest FPGAs, system designers are faced with a formidable system integration challenge. Designs require network connectivity, high speed serial interfaces to share data across chips and boards, memory, power, timing and other resources. Designers need to develop solutions that can be brought to market quickly and efficiently. And there is also a need to develop customized solutions that are uniquely tailored for different markets and customers.

That’s where BittWare comes in. BittWare develops Intel and Xilinx board-level solutions that combine FPGAs with 10/40/100GbE high-speed networking interfaces, PCIe Gen 1, Gen 2 or Gen 3 connectivity, DDR4 memory, Silicon Labs low jitter programmable clocks and a board management controller for advanced system monitoring. The boards are based upon industry-standard commercially-off-the-shelf (COTS) form factors to ensure compatibility and interoperability with chassis and single board computer vendors. The benefit? BittWare’s customers get a turnkey solution that significantly reduces technology risk and accelerates time-to-revenue.

Another challenge is that different applications often require different frequency clocks to support different networking protocols and control plane functions. BittWare and Silicon Labs worked closely together to address this challenge by building support into BittWare’s software so that their customers can directly customize Silicon Labs’ programmable clocks for their own applications. One common hardware platform can be easily adapted to support a broad range of different applications. The hardware, including clocking, is remotely field-upgradable, so new applications can be enabled quickly via software upgrades.

A broad range of markets are benefiting from these system-level turnkey solutions, including broadcast video, finance, instrumentation, government and military/aerospace. In particular, applications like cyber security, high frequency trading, and high-performance computing in data centers require rapid reprogrammability to support innovative new features and services.

By combining Intel and Xilinx programmable FPGAs and Silicon Labs programmable clocks in their designs, BittWare is powering the next wave of innovation in high-speed electronics design.

To learn more about Silicon Labs' timing solutions, click here. 

Date: Thursday, August 30, 2018

Time: 10:00 AM Japan Standard Time

Duration: 1 hour

Design advanced, reliable applications with Silicon Labs’ low-power EFM8 8051-based 8-bit MCUs. Covering solutions ranging from automotive to IoT, we provide industry leading system benefits in terms of performance, size, cost, and power consumption. Get to market faster with advanced tools including integrated IDE, free unlimited code size Keil Compiler, energy monitoring, and advanced debugging.

In this webinar, we explore the advantages of designing with Silicon Labs EFM 8-bit MCUs and identify ideal applications such as automotive, motor control, optical modules, and more.

Last week, the Bluetooth SIG announced an update to the Bluetooth specification in response to a security vulnerability related to Secure Simple Pairing and LE Secure Connections.

According to the SIG, researchers at the Israel Institute of Technology identified that the specification recommends, but does not require, that a device supporting these features validate the public key received over-the-air when pairing with a new device. The Bluetooth SIG has now updated the Bluetooth specification to require the validation of such keys.

At initial connection, when pairing Bluetooth devices, the devices use mutual authentication to securely connect. The SIG has discovered the security vulnerability in the reference implementation of the public key validation during this mutual authentication (https://www.bluetooth.com/news/unknown/2018/07/bluetooth-sig-security-update).

This means that an adversary could perform a man-in-the-middle attack during the pairing process, even for authenticated pairing schemes like numeric comparison or passkey entry. This allows the adversary to listen to and/or modify all the communication on the paired connection.

Our Wireless Gecko products (Blue Gecko and Mighty Gecko) are not affected by this issue because they leverage the mbedTLS ECDH implementation that does not have this vulnerability. The BLE112, BLE113, BLE121LR and BLED112 modules are also not affected because they do not implement the feature that contains the vulnerability. Our BT Classic products, which include the BT111 and WTxx modules, are not affected.

Our BT121 Bluetooth dual mode module is vulnerable to this issue. We expect to release a patch that protects against this vulnerability within 17th August 2018.

It has been postulated that every human is connected to every other human with only six relationships between. It has also been proven that probabilistically, you can be in a room with 23 people and have a 50 percent chance of two people having the same birthday. These connections are all around us. It turns out that digital electronic frequencies seem to have an even tighter relationship when viewed by their fractional relationships.

Rational numbers are numbers that can be written it the form of a + b/c where a, b, & c are all integers. This is a handy way to work with frequencies because of the extensive relationships we have found between seemingly unrelated applications.

Fractional Relationships

At Silicon Labs, we see a lot of seemingly unique frequencies from our customers. Consequently, we are in a prime spot to observe relationships between frequencies.

Recently, we received a request for a Si5338 frequency plan that had the following frequencies:

Input: 185.439560440 MHz

OUT1: 148.5 MHz

OUT2: 148.351648352 MHz

OUT3: 27 MHz

Upon initial inspection, there are no nice fractional relationships between these numbers. When such complex divider values are needed, it limits the ability of our algorithms to optimize the performance. So, we dug in a bit to understand the real source of these high-precision numbers.

First, we noted that some of these frequencies look to be related to the SMPTE standard where the line data rate can be 1485Mbps or 2970Mbps. 27MHz is also used by SMPTE systems. In SMPTE, the fraction 1000/1001 is deployed to avoid interference.

Armed with the customer’s entered frequencies and our knowledge of the SMPTE standards, we begin our detective work:

185.439560440 * 1001/1000 = 185.62500000044

If we can truncate those last two digits, we would have a nice fractional value, but where did those odd values come from. Let’s truncate and find out. Often, we are looking to get to a line rate of something we have seen before. To do so, we often see line rates that are multiples of the clocks by factors of 2, 4, 8, 16, 10, or 20.

185.625000000 * 2 = 371.25

185.625000000 * 4 = 742.5

185.625000000 * 8 = 1485

185.625000000 * 16 = 2970

185.625000000 * 10 = 1856.25

185.625000000 * 20 = 3712.5

Here we have found two SMPTE-related numbers 1485 and 2970. Eureka! So:

185.439560440 is better written as 2970/16/1001*1000 or 185.4395604 4395604 4395604 (repeating)

Armed with our new knowledge, we can apply these fractions and base numbers to take full advantage of our frequency planning algorithms. To enter these values, we have created a frequency editor that can accept equations.

Pulling up CBPro for the Si5338, and proceeding to the input frequency page:

Continuing this for the outputs:

As you can see at the bottom of the window, the frequency plan is valid and the design is ok, which means it has been optimized. Entering the frequencies as they were given, yields an unrealizable plan.

This same frequency entry form is available throughout CBPro for our clock generators, jitter attenuators, and synchronization clock products.

Conclusion

By entering the input and output frequencies as the full fraction values, CBPro can best optimize to achieve the desired synchronous result (no frequency error) with the lowest jitter possible. The frequency editor in CBPro accepts multiplication, division, addition, subtraction, and even PPM addition giving you the easiest path to creating the frequencies you need in your designs. If you are unsure if the relationships exist, we are here to help you.

(CBPro can be downloaded from Silicon Labs website from http://www.silabs.com/cbpro)

In English, we often use the expression “comparing apples to apples” to mean we are making a fair comparison between similar things. On the other hand, if we are “comparing apples to oranges” then we mean the opposite.

Sometimes, despite our best efforts, our lab measurements may yield an instance of “apples to bruised apples”. In this month’s post, I will provide a relatively common example in The Case of the Discrepant Scope Measurements.  

The original case

Years ago, I was supporting an oscillator customer and we were having correlation issues, i.e. his measurements versus mine. His period jitter measurements were just not making any sense compared to the spec and to the part’s typical performance.

I knew enough to make sure that we had similar boards, cables, terminations, test equipment, and were at least attempting the same measurements. We even had very similar oscilloscopes. I was starting to wonder if there really could be something amiss with his device when I asked him to send me a scope shot of his waveform. Bingo! His waveform was a fraction of the size of mine and I knew that was most likely the source of the discrepancy.

Example Lab Measurements

To illustrate the issue I took a nominal 2.5V LVDS 100 MHz output clock and measured it with a good quality 1 GHz DSO or Digital Storage Oscilloscope that supports measurements statistics (the higher bandwidth scopes were all tied up and 1 GHz is sufficient here.) I took each measurement a little over 10K times, varying only the vertical scale, and tabulated the key results below. Note that I record the measurements below in decreasing vertical scale. The smaller the vertical scale, the larger the displayed waveform.

The most notable observation is that the standard deviation of all of the measurements decreased with vertical scale. The smaller the vertical scale, and the larger the displayed waveform, the more accurate the measurements.

One Man’s Noise is Another Man’s Signal …

I am particularly interested in the period jitter, which is the standard deviation of the period measurements. If we plot period jitter versus vertical scale from the table values we obtain the following linear plot.

The measured period jitter versus the scales sampled appears linear. Further, there was no deflection at the smaller values suggesting we were not approaching a measurement “floor”.

Before discussing why the measurements turned out the way they did, let us briefly review the screen caps for each scale selection and why we might use them.

The 250 mV/div selection

This is the smallest displayed waveform selection of the three instances. You run in to this type of scaling when attempting to measure several waveforms simultaneously, for example when comparing relative clock skew. The standard deviation of the period measurements, i.e. the period jitter, was 7.5 ps.

The 100 mV/div selection

This is the most common selection as it is the default or auto scale selection for this particular scope when measuring a single waveform. The period jitter dropped by more than half to 3.2 ps. Great for browsing but as it turns out, still not optimum.

The 55 mV/div selection

This final selection maximizes the displayed waveform on the scope without clipping. The period jitter dropped to about 2 ps.

An Explanation

I purposely did not make any sampling or time scale changes in these measurements in order to eliminate that aspect as a variable. The only change is in vertical scaling which impacts voltage noise. Voltage noise translates to timing noise via slew rate, i.e. the ratio of delta voltage over delta time, as illustrated in the exaggerated figure below. The blue Gaussian curves are intended to suggest normal noise distributions about the decision threshold.

The DSO is a digital scope with a sampling ADC in the front end of the signal chain. The voltage noise will therefore be due to the DUT and the DSO’s ADC quantization noise. This particular scope’s ADC is nominally 8 bits. (The actual ENOB or Effective Number Of Bits may be lower but the principle is the same.)

An 8-bit ADC has 256 unique codes or quantization levels. Therefore, we can compare the nominal quantization levels as follows. There is a significant reduction in quantization noise as we decrease vertical scaling.

The ADC’s 8 bits are employed across the entire vertical display of the oscilloscope so anything less will use fewer bits and result in more quantization noise. This in turn yields more timing uncertainty. It is for this reason that oscilloscope manufacturers often recommend that users maximize the waveform on the screen for most accurate measurements. Doing so without clipping the waveform is the most conservative approach but check with your particular scope vendor.

Conclusion

I hope you have enjoyed this Timing 101 article. Comparing digital scope measurements, which don’t have similar vertical resolution, can result in comparing “apples to bruised apples”.

As always, if you have topic suggestions, or there are questions you would like answered, appropriate for this blog, please send them to kevin.smith@silabs.com with the words Timing 101 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading. Keep calm and clock on.

Cheers,

Kevin

Randy Ferguson joined the Silicon Labs IT team in November 2015 as a desktop support analyst. In his current role as IT service delivery manager, Randy is able to engage with members in all departments, because he and his team are often the first point of contact for company-wide IT support. His responsibilities range from maintaining equipment and infrastructure for day-to-day internal operations, to providing web platform updates affecting external customers. Because of this, Randy said his team has a “unique point of view on the operations of the whole company.” He continued, “we all know that every department is integral to the overall success of Silicon Labs, but working in IT, you really experience it first-hand."

Working in IT also gives Randy the opportunity to see the value of a strong team culture. “Every member of the team is treated like an equal contributor to what we do,” he said. “I’ve always felt that I have the freedom to tackle any task I'm confronted with in the way that suites me best. Being able to trust and rely on your peers’ and leaders’ strengths and cover each other’s weaknesses is something that's hard to come by in my experience.”

“If you haven't met us in person, you might be surprised to find out just how sociable and likeable we can be! That said, we do fly our nerd flags high and proud.” He continued, “We do have a pretty rockin' team in IT, if I say so myself.”

We’re glad to have a rockin’ guy like you on the team, Randy Ferguson. Fly your nerd flag high and keep up the great work!