As a long-time Timing engineer and PCIe advocate, I am happy to share that Silicon Labs recently introduced a new family of PCIe Gen4 compliant clocks and buffers to our existing portfolio of leading PCIe solutions. 

We also released a new, free tool to measure PCIe Gen1/2/3/4 jitter compliance at our PCIe Learning Center. But what is PCIe Gen4 and how is it different than the prior generations?

PCIe Gen4 is a new standardized data transfer bus that will double the data transfer rate per lane of the prior Gen3 revision from 8.0 GT/s (gigatransfers/second) to 16.0 GT/s. This means that a single PCIe Gen4 interconnection will allow data rate transfers of up to 2GB/s (gigabytes/second), and a full 16 slot PCIe Gen4 interconnection for graphics cards and high-end solid state drives will allow data transfer rates of up to 32GB/s.

This increased data transfer rate will facilitate the demanding data transfer rates of new servers and data farms as cloud storage, services, and software become more and more prevalent. It will also allow mobile devices to transfer information super quickly, thus reducing power consumption during downloads or data synchronization activities.

The PCI-SIG is comprised of over 900 companies and has been developing the Gen4 revision since 2011. The standards committee has a rev 0.7 spec available as of December 2015, and the final 1.0 specification will likely be released in 2016. 

The PCIe clocking and buffer requirements are expected to remain unchanged between 0.7 and 1.0; however, one of the options the PCI-SIG is considering is to remove the clocking requirements from the 1.0 specification altogether. This would make clock compliance testing incumbent solely on adopters, who would then measure performance and compliance by measuring the data stream. This would lead to a more challenging debug effort since a key variable would no longer be defined.

While this would give flexibility in budgeting jitter margin between the clock source and transceiver, it would allow inferior clocking solutions to claim PCIe compatibility without any accountability. This would create extra work for users to qualify clock sources, especially when trying to identify multiple sources of compatible clocks and transceivers.

To help customers who are adopting PCIe, we developed the free PCIe Clock Jitter Tool to measure the output jitter of PCIe clocks. This free tool works with any PCIe clock regardless of supplier. It can be found at the Silicon Labs PCIe Learning Center where we have posted multiple PCIe application notes and information on selecting PCIe clocks and buffers.

I hope you will check out the new PCIe learning center, and will find the new PCIe jitter measurement tool useful. Please let us know if you have any suggestions.