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EFM8LB1 reference manual

I  guess this is a copy/paste err\or, but it states that RI can not be cleared when the fifo contain data

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  • Hi Erik,


    Could you tell me where you saw this issue - page number and RM revision? Also, if the receive FIFO is being used, then RI is set to 1 when data is received and stays that way as long as the FIFO is full. Once it is empty hardware clears the bit, so it makes sense that RI cannot be cleared when FIFO contains data. 



  • in the SCON definition


    there is no mention anywhere else of a UART FIFO

  • Got it. You were talking about UART0 and I was thinking UART1. I'll make a note of this. Thanks for letting us know.