Pardon me if i am asking this question on the wrong board.
We are using SI5338 clock generator to provide single ended clocks to two of the devices we are using . One is TLK2711 and the other one is microchip's FPGA (RTG4). TLK2711 has max clock jitter pk-pk requirement as 40 ps but we are not able to meet it through SI5338. When we tried to measure the jitter of the clock from SI5338, its PJrms value is 17.4 ps which if we multiply to Crest factor of 14 (as applicable for the bit rate of 1e-12 for clock signals) gives us peak to peak value of 243.6 ps (way higher than the TLK2711 data sheet specification of 40 ps).
SI5338 datasheet says period jitter max value is 30 ps pk-pk and we are getting nowhere close to this.
Any suggestions or ideas what we are missing here?
Sir or Madam,
Your question here was sent to the Isolation support team. I'll create a Sales Force ticket and transfer it to the correct, TIMING, team.