Anecdotally, on past projects, I've noticed many chips that have ADCs that consistently read on the order of ~10 counts low. The accuracy requirements for these past projects weren't that great so we've generally just lived with it. (10 / 4096 is only about 0.25%.) On one project, I've even applied a slight adjustment to the calculation by taking the reference to be 1.26V. I'm more concerned about the accuracy on my current project so I've dug into it a bit and I'm just wondering if this is normal or if there's something we are doing incorrectly that may improve the situation.
Presently, I have 4 custom boards with EFM32LG232F256 parts. They are powered with 3.3V using the decoupling topology given in Figure 1.3 of AN0002. (We don't usually use this topology but have done so on this board in the hopes of improved accuracy.) The coupling capacitors are literally as close to their respective VDDA and VDD pins as physically possible.
I can apply a constant voltage to one of the ADC pins and sample it with the internal 1.25V reference, x16 oversampling, 128 acquire cycles and no RC filter. The hfperclk is 14MHz and the prescaler is set to 4 (for a 3.5MHz ADC clock).
This results in ADC0 register values of:
CTRL 030D0300 SINGLECTRL 00700730 CAL 380B380B ADC0CAL0 3806380B
I measured 2 constant voltages on each of the four boards and got the following results. The voltage is measure directly on the EFM pin. The ADC reading is taken using a single sample with the settings provided above. The ambient temperature during testing was 22C. The micro should be in EM1 while waiting for the sampling to complete.
BOARD VOLTAGE EXPECTED ADC READING COUNT ERROR PER SAMPLE 1 0.5442 0x6F74 0x6eCB -10.5 1 0.7134 0x921B 0x916C -10.9 2 0.5442 0x6F74 0x6ee0 -9.25 2 0.7136 0x9225 0x9178 -10.8 3 0.5444 0x6F7E 0x6F7C -0.125 3 0.7138 0x9230 0x922C -0.25 4 0.5443 0x6F79 0x6F4D -2.75 4 0.7137 0x922A 0x9231 +0.44
In summary, boards 1 and 2 are each reading about 10 samples low and boards 3 and 4 are pretty much bang on. These results are consistent and repeatable.
I've looked at the VDDA power rail on one of the afflicted boards and there does not appear to be any significant noise during measurements. I've also tried stacking additional caps on both the VDDA and VDD lines with no effect. (I added ~20uF to each rail.) I've also tried changing the acquire time as well as the TIMEBASE value in the control register.
I've ensured the CAL registers are being loaded correctly on all boards and, if these are useful, I've included the value from the DEVINFO table for each of the 4 boards:
BOARD 1V25 CAL 1 0x380B 2 0x426A 3 0x3776 4 0x357C
So, I'm not sure what to think here. Is this typical? Could there be something wrong with our design? I think our software is correct. However, I'm fairly positive I've seen this same 10 counts low problem on other designs with different EFM devices.
At this time, I don't want to have to calibrate the ADCs ourselves and would probably sooner live with the error than increase the production cost in doing the calibration.
Given that the ADCs are factory calibrated I'd have expected a tighter result. The datasheet for the part seems to indicate a higher accuracy (0.033%/C gain error and <1 LSB offset error).
The data sheet numbers are not not entirely accurate here. Especially the offset voltage is misleading. Right now we specify 0.3V typical offset after calibration, but there is no max number. We do calibrate the ADC in production, but in production test we accept parts with significant larger offset than 0.3V. I don't have the exact numbers right now, but the parts you have at -10 ADC codes should be in the extreme range, but could still pass production test.
We are working on improving the data sheets regarding this. Keep in mind that this is an extreme low power ADC, not an extremely accurate one. But we definitely have to improve the data sheets on this point.
Ok, that answers that.
I did some more playing around here and have found some more interesting things.
I've found that by subtracting 10 from the SINGLEOFFSET field in the CAL register an afflicted board will be fixed for a wide range of the ADC so it is indeed an offset error and not a gain error.
However, if I measure the DIFF0 input (as suggested in the offset calibration procedure of the reference manual) it reads zero when the CAL register is the calibrated value and ~10 when I subtract 10. Additionally, reading the single ended VSS input also reads 10 after subtracting.
So it seems that on some chips there is a different offset for single ended measurements than there is for differential and it shouldn't be difficult to calibrate it out.
Thanks for the feedback! We will look into this.