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      • The comparison about voltage selection of LCD module between Series 0 and Series 1 devices

        yucheng | 11/313/2017 | 07:01 AM

        There are some EFM32 device families support LCD be listed below, and some detailed functionality is different depending on the device. This article will show a comparison about the VLCD selection between Series 0 device EM32TG and Series 1 device EFM32GG11.

        MCU Series 0 devices support LCD:

        • EFM32 Gecko (EFM32G)
        • EFM32 Giant Gecko (EFM32GG)
        • EFM32 Wonder Gecko (EFM32WG)
        • EFM32 Leopard Gecko (EFM32LG)
        • EFM32 Tiny Gecko (EFM32TG)

        MCU Series 1 devices support LCD:

        • EFM32 Giant Gecko (EFM32GG11)

         

        VLCD Selections for Series 0 device:

        Below is the LCD Block Diagram of Series 0 device EFM32TG, for simplicity, only one segment pin and one common terminal are shown in the figure.

        As illustrated in the Figure above, there are total three power selections for LCD, main external power, internal boosted voltage or dedicated power supply.

        By default, the LCD driver runs on main external power (VLCD = VDD), marked as ① in the Figure above.

        The second ② selection is internal boost circuit, it can be enabled by setting VBOOSTEN in CMU_LCDCTRL and selecting the boosted voltage by setting VLCDSEL in LCD_DISPCTRL. This will boosts VLCD to VBOOST which can be selected in the range of 3.0 V – 3.6 V by configuring VBLEV in LCD_DISPCTRL when VDD is as low as 2.0V. Note that the boost circuit is not designed to operate with the selected boost voltage, VBOOST, smaller than VDD. And when using the voltage booster, the LCD_BEXT pin must be connected through a 1 µF capacitor to VSS, and the LCD_BCAP_P and LCD_BCAP_N pins must be connected to each other through a 22nF capacitor.

        The third ③ selection is that power the LCD module with a dedicated power supply. The dedicated power supply must be connected to the LCD_BEXT pin and VLCDSEL in LCD_DISPCTRL must be set. And the voltage booster should be disabled in this mode.

         

        VLCD Selections for Series 1 device:

        An overview of the LCD module for Series 1 device EFM32GG11 is shown in Figure below, similar as before, only one segment pin and one common terminal is shown in the figure.


         
        There are three modes are available for setting the VLCD level be controlled by the MODE field in LCD_DISPCTRL: current source mode, step down mode, or charge pump mode.
        For the current source mode (marked as ① in the Figure above) no external capacitor is used. An internal current source is adjusted using CONTRAST[4:0] in LCD_DISPCTRL to set the VLCD voltage level.

        For the step down mode ② an external capacitor is regulated using an LCD comparator to maintain a VLCD voltage that is not greater than the supply voltage.

        For the charge pump mode ③, a voltage of up to twice the supply voltage is generated internally and maintained on an external capacitor, which maintains the VLCD voltage.

        In both the step down and charge pump modes, the LCD_BEXT signal is used. The LCD_BEXT pin should be connected through a capacitor to VSS. For most applications, a 1 µF capacitor is sufficient to prevent any visible artifacts from supply ripple. However, larger capacitors may be used to reduce the supply ripple if needed. The recommended value is approximately 1000 times the total LCD segment capacitance.
         

      • Endianness of Silabs EFM32/EFR32/EZR32 devices

        delu | 11/312/2017 | 08:40 PM

        Question
        Can I choose big-endian mode on EFM32? If yes, How?
         

        Answer
        We cannot select big-endian mode on EFM32.

        Endianness is a design time instantiation option on ARM Cortex-Mx cores, and you will find that the Endianness status bit in register bitfield SCB->AIRCR is hardwired to 0 for every Silabs Cortex Mx series product.
         
        Refer to Arm link page here. You could use below code snippet to get the endianness that Silabs 32-bit MCU used:
         

          uint32_t endianness;
          endianness = SCB->AIRCR & SCB_AIRCR_ENDIANESS_Msk;


         

      • Voltage scaling on EM0/1 of EFM32xG11/12/13

        amenleung | 11/306/2017 | 10:49 PM

        Voltage scaling is supported on EFM32xG11/12/13 devices and below example is to scale voltage down and up on  EM0/1.

          // HFCLK must be < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX (20 MHz) before scaling down
          CMU_HFRCOBandSet(cmuHFRCOFreq_19M0Hz);
        
          // EM0 and 1 initialization structure
          EMU_EM01Init_TypeDef vsInit;
        
          // Scaling down from VSCALE2 (1.2 V) to VSCALE0 (1.0 V)
          vsInit.vScaleEM01LowPowerVoltageEnable = true;
          // Flash wait state at VSCALE0 will be set during scaling voltage down 
          EMU_EM01Init(&vsInit);
        
          // Scaling up from VSCALE0 (1.0 V) to VSCALE2 (1.2 V)
          vsInit.vScaleEM01LowPowerVoltageEnable = false;
          // Flash wait state at VSCALE2 will be restored during scaling voltage up 
          EMU_EM01Init(&vsInit);
        
          // HFCLK can now be restored after scaling up
          CMU_HFRCOBandSet(cmuHFRCOFreq_26M0Hz);
        

         

      • EFM32xG11/12/13 power mode scaling time

        amenleung | 11/306/2017 | 09:35 PM

        Power mode scaling is supported on EFM32xG11/12/13 devices.

        Time to scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 μs + 29 HFCLKs.

        It is `4.3 μs if the HFCLK is 19 MHz.

        Time to scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 μs + 28 HFCLKs.

        It is ~31.8 μs if the HFCLK is 19 MHz.

        There is an emlib function EMU_VScaleWait() to wait for voltage scaling to complete.

      • Segger emWin part numbers in Gecko SDK

        Stephen | 11/305/2017 | 05:08 PM

        Question

        What Segger emWin components are included in the Gecko SDK suite?

        Answer

        The following Segger emWin part numbers are provided in the Gecko SDK suite:

        • 3.50.04 emWin PRO, which includes:
          • 3.00.01, emWin BASE color
          • 3.01.00, emWin WM/Widgets
          • 3.01.02, emWin Memory Devices
          • 3.01.03, emWin Antialiasing
          • one driver: 3.10.02, GUIDRV_Lin

        The complete list of emWin part number can be found on this webpage: https://www.segger.com/purchase/pricing/emwin/

        If additional emWin part numbers are required for your development or application, please contact Segger.

      • EFM32 and EFR32 Series 1 UNIQUEH and UNIQUEL registers

        Stephen | 11/305/2017 | 11:52 AM

        Question

        What values are stored in the UNIQUEH and UNIQUEL registers on EFM32 and EFR32 Series 1 devices?

        Answer

        This knowledge base article applies to EFM32 and EFR32 Series 1 devices, such as

        • EFR32MG1, MG12, MG13
        • EFR32BG1, BD12, BG13
        • EFR32FG1, FG12, FG13
        • EFM32GG11

        The UNIQUEH and UNIQUEL registers are located on the Device Information (DI) page. Together, this is also known as EUI64. Starting with the most significant bit, the construction is formed by concatenating:

        OUI (Organizationally Unique Identifier) [23:0]

        + 0xFFFE

        + EUI48L.UNIQUEID [23:0]

        where EUI48L.UNIQUEID is a unique number pulled from a pool for a specific OUI, stored in the EUI48L register.

        ----

        Simplicity Commander can be used to read the DI page. The 01 E5 00 FE FF 57 0B 00 value below shows EUI64 starting with the least significant byte:

        $ commander readmem --range 0x0FE081B0:0x0FE081FF
        Reading79bytes from 0x0fe081b0...
        {address:0123456789  A  B  C  D  E  F}
        0fe081b0: D4 BA 1F FF FF FF FF FF FF FF FF FF FF FF FF FF
        0fe081c0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
        0fe081d0: FF FF FF FF FF FF FF FF 01 E5 00 57 0B 00 FF FF
        0fe081e0: FF FF FF FF 00 4D 30 01 12 11 11 00 07 00 00 00
        0fe081f0: 01 E5 00 FE FF 57 0B 00 00 01 20 00 E9 00 10 --
        DONE

        where

        0x0fe081b0 = DI page starting address 
        01 E5 00   = EUI48L.UNIQUEID [23:0]
        FE FF      = 0xFFFE
        57 0B 00   = OUI (Organizationally Unique Identifier) [23:0]

        ----

        The EUI64 can also be determined using the Simplicity Commander “device info” command (most significant bit is displayed first):

        $ commander device info
        Part Number   : EFR32MG1P233F256GM48
        DieRevision   : A1
        ProductionVer : 130
        FlashSize     : 256kB
        SRAM Size     : 32 kB
        UniqueID      : 000b57 fffe 00e501
        DONE

         

      • EFM32 and EFR32 Series 1 EUI48H and EUI48L registers

        Stephen | 11/305/2017 | 11:44 AM

        Question

        What values are stored in the EUI48H and EUI48L registers on EFM32 and EFR32 Series 1 devices?

        Answer

        This knowledge base article applies to EFM32 and EFR32 Series 1 devices, such as

        • EFR32MG1, MG12, MG13
        • EFR32BG1, BD12, BG13
        • EFR32FG1, FG12, FG13
        • EFM32GG11

        The EUI48H and EUI48L registers are located on the Device Information (DI) page. Together, this is also known as EUI48. Starting with the most significant bit, the construction is formed by concatenating:

        Reserved [15:0]

        + OUI (Organizationally Unique Identifier) [23:0]

        + EUI48L.UNIQUEID [23:0]

        where EUI48L.UNIQUEID is a unique number pulled from a pool for a specific OUI.

        ----

        Simplicity Commander can be used to read the DI page. Starting with the least significant byte, the EUI48 is 01 E5 00 57 0B 00 FF FF as shown below:

        $ commander readmem --range 0x0FE081B0:0x0FE081FF
        Reading 79 bytes from0x0fe081b0...
        {address:  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F}
        0fe081b0: D4 BA 1F FF FF FF FF FF FF FF FF FF FF FF FF FF
        0fe081c0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
        0fe081d0: FF FF FF FF FF FF FF FF 01 E5 00 57 0B 00 FF FF // last 8 bytes on this line
        0fe081e0: FF FF FF FF 00 4D 30 01 12 11 11 00 07 00 00 00
        0fe081f0: 01 E5 00 FE FF 57 0B 00 00 01 20 00 E9 00 10 --
        DONE

        where

        0x0fe081b0 = DI page starting address
        01 E5 00   = EUI48L.UNIQUEID [23:0]
        57 0B 00   = OUI (Organizationally Unique Identifier) [23:0]
        FF FF      = Reserved [15:0]
      • EFM32 SPI Slave and Master examples with emdrv SPIDRV

        yucheng | 10/303/2017 | 04:53 AM

        The SPI driver support the SPI capabilities of EFM32/EZR32/EFR32 USARTs. The driver is fully reentrant and several driver instances can coexist. It provide two kinds of transfer functions, synchronous and asynchronous. Synchronous transfer functions are blocking and will not return to caller before the transfer has completed. Asynchronous transfer functions report transfer completion with callback functions. All of the transfers are done using DMA.

        Take EFM32PG1B as example to demonstrate how to initialize the USARTs as SPI mode. EFM32PG1B has two USARTs, the example show how to initialize USART0 as a SPI Slave, and initialize USART1 as a SPI Master with emdrv (SPIDRV), it's the easiest way to demonstrate the SPI without connecting any external components but just need to connect the corresponding port pins between SPI Slave and Master. Please refer to the SPIDRV_SLAVE_USART0 and SPIDRV_MASTER_USART1 config structure for the port pins location information.

        After finishing the SPI initialization, SPI Slave will start a few bytes transmitting by calling an asynchronous function SPIDRV_STransmit() which will be returned soon, the callback function will be executed once the DMA finished the transfer. SPI Master will start the receiving transfer by calling an synchronous function SPIDRV_MReceiveB(), it will not return until received specified length of data from Slave.

        For the SPI Slave receiving case, it will start the SPI slave receive transfer in non-blocking, and the data transmitting from the Master will caused the report of receiving transfer completion with callback function.

          // Start a SPI slave transmit transfer
          SPIDRV_STransmit( handleSlave, slaveTxBuffer, sizeof(slaveTxBuffer), slaveProcessTxDone, 0);
          // Receive data using a blocking receive transfer
          SPIDRV_MReceiveB(handleMaster, masterRxBuffer, sizeof(masterRxBuffer));
        
          // Start a SPI slave receive transfer.
          SPIDRV_SReceive( handleSlave, slaveRxBuffer, sizeof(slaveRxBuffer), slaveReceiveComplete, 0);
          // Transmit data using a blocking transmit function
          SPIDRV_MTransmitB(handleMaster, masterTxBuffer, sizeof(masterTxBuffer));

        Attached is the example code of EFM32PG1B for the SPI Slave and Master transfer on emdrv (SPIDRV).

         

      • Driving the HFXO with an active external digital clock source

        yucheng | 10/296/2017 | 02:18 AM

         

        By default the HFXO is started in crystal mode, but it is possible to connect an active external sine wave or square wave clock source to the HFXTAL_N pin of the HFXO. By configuring the MODE field in CMU_HFXOCTRL to EXTCLK, the HFXO can be bypassed and the source clock can be provided through the HFXTAL_N pin.

         

        And what the KB discussed is the external digital clock, for how to use the external sine wave, please refer to AN0004 for more information.

         

        A rail-to-rail square wave with 50% duty cycle can be applied to the HFXTAL_N pin, and the frequency should in the range of 38 MHz - 40 MHz which is same as a crystal connected to the HFXO. When clock is provided via HFXTAL_N, the HFXTAL_P can be used for other functionality.

         

        For using the external digital clock source, initialize the HFXO with the default structures CMU_HFXOINIT_EXTERNAL_CLOCK which be defined in the em_cmu.h

         

         

          CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_EXTERNAL_CLOCK;
        
          /* Init HFXO with kit specific parameters */
          CMU_HFXOInit(&hfxoInit);
        
          /* Switch HFCLK to HFXO and disable HFRCO */
          CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
          CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);

         

         

        #define CMU_HFXOINIT_EXTERNAL_CLOCK                                            \
          {                                                                            \
            true,       /* Low-power mode */                                           \
            false,      /* @deprecated no longer in use */                             \
            false,      /* @deprecated no longer in use */                             \
            false,      /* @deprecated no longer in use */                             \
            0,          /* Startup CTUNE=0 recommended for external clock */           \
            0,          /* Steady  CTUNE=0 recommended for external clock */           \
            0xA,        /* Default shunt steady-state current */                       \
            0,          /* Startup IBTRIMXOCORE=0 recommended for external clock */    \
            0,          /* Steady  IBTRIMXOCORE=0 recommended for external clock */    \
            0x6,        /* Recommended peak detection threshold */                     \
            0x2,        /* Recommended shunt optimization timeout */                   \
            0x0,        /* Peak-detect not recommended for external clock usage */     \
            _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */   \
            _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
            cmuOscMode_External,                                                       \
          }

         

        And if needed, then rework your board to remove the crystal oscillator, and connect the active external clock to the HFXTAL_N pin.

         

        First time when enable an external clock we should set the CMU_CMD register to make sure that we only do Shunt Current Optimization (SCO) and not Peak Detection (PDA) tuning. Attached is the example code of EFM32PG12 for how to use the external digital clock source to drive the HFXO.

         

      • DPLL on MCU Series 1

        amenleung | 10/282/2017 | 04:42 AM

        Question

        What is the usage of DPLL?

        Answer

        The Digital Phase-Locked Loop (DPLL) uses the HFRCO to generate a clock as a ratio of a reference clock source.

        The reference clock source (FREF) can be HFXO, CLKIN0, LFXO, or USHFRCO (if available).

        Output frequency = FREF*(N+1)/(M+1), where N and M are 12-bit values in CMU_DPLLCTRL1 register.

        The DPLL is not available on EFM32xG1 and EFR32 devices.

         

        Code example on EFM32PG12:

         

         

        // Enable LFXO and wait it ready, use as DPLL reference clock
        CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
        
        // Setup target HFRCO frequency, factor N and M 
        CMU_DPLLInit_TypeDef dpllInit = CMU_DPLL_LFXO_TO_40MHZ; dpllInit.frequency = 36864000; dpllInit.n = 2249; dpllInit.m = 1; // CMU_DPLLLock() will update flash wait state and SystemCoreClock for target HFRCO frequency if (!CMU_DPLLLock(&dpllInit)) { // DPLL lock failed while (1); }