Silicon Labs Precision 32 and 8-bit MCUs use SAR architecture ADCs. In this architecture, an array of capacitors, each having a value proportional to one bit of the output code, is charged to the sample voltage. These capacitors are then used, along with VREF, as a capacitive DAC to feed into a comparator, which outputs a 1 or 0 as each of the capacitors in series are switched to VREF or GND. For a thorough explanation, see the In-Depth SAR Analysis section of the following application note: http://www.maximintegrated.com/en/app-notes/index.mvp/id/1080
In the normal case, all of the capacitors are charged to the sample voltage, VIN. When the MSB capacitor is switched to VREF, the voltage on the comparator's negative terminal , CMP-, becomes -VIN + 1/2 VREF. If this value is higher than GND, the value of the comparator is zero. In this case, the capacitor is switched back to GND, so the voltage on CMP- becomes -VIN again. The next capacitor in the series is then switched, causing CMP- to be -VIN + 1/4 VREF. This process is repeated for each capacitor, until all bits have been compared.
The ADCs in the Precision 32 and 8-bit MCUs also have a PGA gain, which can be set to 1 or 0.5. Setting this to 0.5 practically doubles VREF, so a larger range of voltages can be measured. The way this is implemented is by incompletely charging the sampling capacitor array. In the case of 0.5 gain, the MSB capacitor is not charged. When the MSB is initially connected to VREF, the voltage on CMP- then becomes -1/2 VIN + 1/2 VREF rather than -VIN + 1/2 VREF. This halving of VIN effectively doubles the range of VREF.
Since this gain mechanism is merely charging half of the sampling capacitance, it is very precise, and behaves essentially the same as gain = 1 across temperature, supply voltage, etc.