How do I set the VDD monitor threshold?


Some MCUs have two VDD Monitor levels that can be selected: low threshold monitor lever and high threshold monitor level. Examples of these devices are C8051F500, C851F530, C851F540, and C851F550.


Silicon Labs strongly recommends that the VDD Monitor is always left in the low threshold setting. The reason is that the output of the internal voltage regulator is calibrated by the MCU immediately after any reset event, and the output of the un-calibrated internal regulator could be below the high threshold setting of the VDD Monitor. The MCU will receives a non-power on reset, VDD Monitor will keep the MCU in reset until a POR occurs. A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the uncalibrated output of the internal regulator. The device will then exit reset and resume normal operation.


However, if the system clock frequencies greater than 25 MHz, the VDD monitor level should be set to the high threshold to prevent undefined CPU operation. The high threshold should only be used with an external regulator powering VDD directly, not the internal voltage regulator.  The figure below illustrates the recommended power supply connections. The VDD and VDDA voltages must be 2V or higher and greater than the VDD monitor high threshold.




The electrical characteristics about VDD / VDDA voltage and reset threshold can be found within the Electrical Charateristics section of the datasheet. An excerpt is shown below.




When programming the Flash in-system, the VDD Monitor must be set to the high threshold setting. For the highest system reliability, an external voltage regulator should be used. If this is not possible, the time the VDD Monitor is set to the high threshold setting should be minimized.

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