Why does changing the PGA setting from, say, 8 to 32 increase the current consumption of the circuit?
The PGA on a SigmaDelta ADC like the one on C8051F353 is usually implemented with CMOS switched capacitors. Essentially, there is a capacitor of a certain size that is being switched in and out at a certain frequency. This creates a variable resistor that can be scaled with frequency or capacitor size, relative to another reference capacitor in the design. The variable resistor is how we adjust the gain of the PGA.
For certain gain settings, we scale the capacitor size and the for higher gain settings (over 8x), we adjust the frequency of the switched cap. The extra supply current is probably clock current going to those switched capacitors, and some from the switches themselves, being switched at a higher frequency.