I am able to perform most operations including reading the serial number, reading device state reading temperature and reading humidity in No-Hold master mode.
When I read the humidity in Hold Master Mode I observe the clock stretching for 15.8 ms then the clock is released and the data line is still held low by the Si7006-A20 device. This continues essentially forever. If I pulse the clock line (seconds later) the data line is released.
Any hints or suggestions as to why this happens, I expected the device to not try and control the data line until after the clock next went low in this situation.
Are you seeing the ACK after writing the address before expecting the clock stretching? SDA can be held low if something unexpected occurs, such as an extra clock pulse or bad data is written.
I think this might be normal.
With the command 0XE5 the Si7006 will hold the clock low until the conversion is complete. Then it will drive the SDA line low if the first bit is zero basically waiting for clock pulses to drive data. The rising edge of SCL that happens when we release SCL is the rising edge of the clock for the first data bit (MS bit of the data) so we need to drive SDA low as soon as we are ready. If the MS Bit of the data we are trying to produce is zero then it is perfectly normal for SDA to be held low.
The setup write of 0xE5 and the subsequent read initiation appear normal. There is an ACK to the read.
I see that there is an ACK to the read (SDA low) and then the clock stretch. SDA is held low in the clock stretch. There is no spec about this - while SCL is low, SDA can be high or low. You mentioned that at the end of the clock stretch SDA is held low until the next time the clock goes high. All this this means is that we are clocking out a zero on the first clock pulse. If we were trying to clock out a 1 we would release SDA when we release the clock line.
I had to think about this a while so I can appreciate that it is confusing. When we release SCL, this is the rising edge of the first clock pulse for data. The master should have already released SCL and assuming the master can deal with clock stretching, it should be waiting for the clock to go back high so it can clock in the first bit of the data and then pull SCL low to set up for the next bit.
SDA high or low when we release the clock line is simple a matter of what data we are trying to clock out.
I will admit it is a little surprising that we hold SDA low then release it when we release SCL. You might think it would be the other way where we release SDA in the clock stretch period and then pull SDA low if we are trying to clock a zero. I think whether or not we release SDA in the clock stretch time is a matter of what data we sent last time. In any case, from the perspective of I2C spec compliance it does not matter if we hold SDA low or release SDA while we stretch the clock we just need to pull SDA low when we release SCL if we are clocking a zero or release SDA when we release SCL if we are clocking a 1.
Some masters do not deal with clock stretching well and clock stretching can cause extra power. For these situations we recommend the no hold master command. If your software would not deal well with a NACK while we do the conversion then put in a timer so that the conversion will be complete and we will ACK when you read the result.
Thanks for the insights. The Arduino i2C support does claim to handle clock stretching. My current suspicion is that the support has a timeout that is less than the 16ms or more that we are seeing. There is discussion in the ESP8266 forum that supports this theory, but, I have not validated it completely.
Reading using No Hold Master Mode works fine for me, so I'll just stick with that.
An even better solution for my application would be to have a way to initiate a read, terminate the I2C command and come back later to poll for completion of the measurement. The data sheet does not seem to have a way of doing this, all of the examples expect a Repeated Start prior to reading the data. The sequence would be a write of the command with normal ACK and stop bits. Then do a read which might NACK if the data is not ready. The I2C bus might be used by others between the write and the read.
With the no hold master command, you can send the command for a conversion and then end with an optional stop and then wait an arbitrary amount of time and do other stuff on the bus to other devices until you read the data. If you send our address we will NACK it until the conversion is complete and the data is ready.
The only issue is that after you send the command, we consume an excess current of about 20uA until you read the data.
Great, that might be a good thing to put into data sheet errata.
Yes we are working on that. Thanks