On the SI56361 datasheet electrical specification,
Table 3.2 indicates :
-LVCMOS Input High Voltage VIH VDD x 0.7 V
-LVCMOS Input Low Voltage VIL VDD x 0.3 V
Meaning that clock level shall be under VDD x 0.3 V (for low level), and over VDD x 0.7 V for (high level). So more than 1.32Vpp when VDD is 3.3V.
Table 3.6, additive jitter is given for Vin Peak-to-Peak amplitude at 0.15 and 0.5 V.
Is there a mistake or does the circuit really operate with such low input level voltage?
In such case, is Clk in internaly polarized ? Can we connect the inputs with capacitors ?
Thanks for your help