This Community thread is for feedback on the new Silicon Labs PCIe Clock Jitter Tool. The tool was recently announced and is available as a free download here:
We are very excited for people to try it out! Please let us know any feedback or suggestions that should be addressed in future updates.
Silicon Labs Timing Support Engineers
Very Nice tool with excellent reports!
I have some scope captures CSV files that I've used with "other" PCIe Clock Jitter tool. They don't work with this tool. They are amplitude only with a fixed sample interval. In this case the sample interval is 25pS.
Do you have plans to support these?
I've pasted an example of the file:
The PCIe tool currently supports digitized waveforms and interval files. The file you have is a form of digitized waveform with the timebase specified in the header which we do not yet support.
Although cumbersome, it is possible to modify these data files to work with the current version of the tool. The tool is expecting a 'time,amplitude' format for digitized waveforms so you could add a column of timestamps to the file that are 25ps apart for each successive amplitude measurement.
We now plan to add this file format to a future revision of the tool. Thanks for bringing it to our attention! Please be sure to 'watch' this thread and we'll post a notification here when the update is released.
Attached is a simple Python script to add time data to a file that only contains amplitude data. This script requires numpy and pandas to be installed. It can be easily modified to change the number of header rows in the amplitude file and also to change the timebase (default is for 2 header rows and 25ps data).
I was unable to use the attached 'wfm' file with the SI PCIe Clock Jitter Tool. It says 'Error processing wave data'. Please ensure you have selected the correct file format. Use the back button to review your selections.
I had selected: Time Domain, Differential, Edge filtering(checked) with the waveform. Is there an email address to send the file to. It is taking a lot of time to upload on account of its size.
Can you please send the scope settings you used to create the waveform file ?
i.e. time base, sampling rate, clock frequency (of the clock you measured on ) and the memory depth ?
Please review the application note AN952 from us to ensure that your set up is compliant with the PCIe requirements.
Updating this thread with new information as we discover it ...
When correlating the Silicon Labs PCIe Clock Jitter Tool to the PCI-SIG tool from Intel, it is necessary to turn off the 'Edge Filtering' option. This option is enabled by default in the Silicon Labs tool but not enabled in the PCI-SIG tool. For best correlation results be sure to disable 'Edge Filtering'.
Also, when capturing waveform data on a high-bandwidth scope like the Keysight DSA90xxx series be sure to enable the 'sin(x)/x interpolation' option. This scope option ensures the digitized waveform most accurately represents the actual PCIe clock waveform.
What is the edge filtering option?
When I run data through with the edge filtering off, I get failures. If I turn it on, it passes.
Also, when I push through a data set with 10ps sample interval, it will pass. When I remeasure at 40ps sample interval, it fails (HF RMS) for Gen 3. What is the minimum sample interval necessary?
We have been using the Si5338 as clock source for several PCIe products with very good results. Long/lossy links have been stable and error free for years. So I believe our implementation is good.
The clock is connected with two coaxes directly to the scope and the eye diagram as measured with the scope is super-clean in infinite persistence.
When using the PCIe Clock Jitter Tool, I'm seing strange results with big data sets from a Lecroy Waverunner 8404. The Waverunner reports nothing suspicious regarding min/max edge rates, but the Jitter Tool reports increasingly higher edge rates the bigger a data set is. in a 200k edges data set, the tool reports an average edge rate of about 2.0 V/ns, and a max edge rate of almost 26 kV/ns...
Also there is significant stepping in the TIE, Period, and Cycle-Cycle waveforms.
Hope you can look into this, as the tool is really useful. I've attached the report output.
I can provide scope data files on request.
I'm not 100% sure that this is jitter tool issue. It may be SI issues, or scope issues as well. But as the scope measurements ar so different from the Jitter tool measurements, I'm posting here first.
I was wondering if you could tell me about what edge filtering is? What does it overcome? Also, how have you implemented it?
The edge filter is a 5GHz first order low pass filter prescribed by PCIe-SIG.
This edge filter is useful in the following way:
1. It removes any high frequency noise (usually on the rising/fall edges of the clock) above 5 GHz i.e. it smoothens the rising/falling edges which helps reduce noise that can lead to errors when detecting the "zero-crossing"
We have implemented it as stated above, as a 5GHz low pass filter (in time domain) before we detect periods based on zero crossing detections.
In the older implementation of the PCIe jitter tool, this is a "selectable" option along with SSC separation.
In our latest implementation of PCIe jitter tool, these are automatic i.e. the user need not enable/disable any of these.
Please download the latets version (or upgrade to the latest version if you are using our older version).
1) Is it applicable for all data rates or only gen1/gen2 obviously?
2) Is there a plan to roll this for all data rates and if so what would be the passband of this filter?
3) I couldnt find it in the spec, where the 5GHz low pass first order filter is specified. Can you give me a version number and page number if possible?
4) What problem is it trying to solve? Spec says 'edge filtering is to be used to counter measurement induced jitter due to finite sampling rate of the instrument'. What do you make of this?
1. This is applicable to all data rates.
2. This is a "low pass filter" which means that a 5GHz pass band is present. A
3. You can find the edge filtering BW specs in PCIe base specifications release v3.0. In 4.0, the edge filter is mentioned but there is no BW mentioned and we (Si Labs) verified with PCIe-SIG that the 5 GHz BW still is true.
4. Edge filtering benefits are illustrated in the attached picture.
Thanks a lot Hari. That was very helpful.
I have a further question, is the jitter seen at the edge an artifact of the finite sampling rate of the instrument?
Also, the spec refers to an 'voltage averaging process applied at a frequency of 5 GHz'. Is this what you are referring to(in the spec)? How could this be the same as a low pass 5GHz filter?
1. The jitter is not an artifact of the sampling rate of the scope. The finite sampling rate "increases" quantization noise which increases "noise floor". The edge filter is used to smoothen any signal integrity impact such as reflection on T-lines, interference due to power supply switching on the same board as DUT and so forth.
2. No for the voltage averaging. I meant that the edge filter's cut off frequency.