I am using a Silicon Labs SI5319 PLL on my design
My input is 2.048 MHz CMOS and I need a clean 44.7360 MHz CMOS output that is synchronized
to the input. My reference is a 114.285 MHz crystal. Can you ask someone for the proper register settings to achieve this?
I am in a hurry for this info. I tried using the software, but my output is not tracking the input.