I'm working on a FPGA board using a SI5338 for clock interfacing. In the current configuration CLK0 is fed directly by IN1/IN2 - refclk (PLL bypass).
Now I want to use an alternative clock source, connected to IN5/IN6 for the CLK0 output, also bypassing the PLL. I wonder if the whole configuration process, as described in the data sheet, will be required? Shouldn't it be sufficient to disable the output, change register 31 from refclk to fbclk and enable the output again?
Are the register bits given in section 10.2 of the reference manual vital for reconfiguration in this case?
It depends on how you are using the entire part. If other internal functions are being used then it's best to go through the entire re-configuration process to avoid unintended interactions. For example, if the LOS alarm/interrupt is being used then switching to a different input will require changing the LOS configuration. Even if not using the LOS interrupt, an internal LOS alarm event will squelch the outputs.
Please excuse the delayed answer.
A support agent contacted me, and it seems as bypassing the PLL allows a very simple multiplexer-like configuration of the SI5338. I gave it a try, and it worked as expected.
However, this is just for prototyping and eventually we will dig deeper into the SI5338 to verify no unwanted side-effects occur.