I want to confirm the guarantee of the following operation using Si5351 series.
- Si5351 creates 3 clocks for audio device, master clock (MCLK), bit clock (BCLK), frequency clock (FCLK)
- The frequency of these clocks must be fine adjusted (e.g. +-500ppm) at the same moment during audio device working (on the fly). No irregular waveforms at the transition are not accepted.
- The edge of these clocks must be aligned.
- XTAL and PLLA of Si5351 device is used.
- Initialize with center frequency with no phase offset for all audio clock output, then execute soft reset via I2C
- For fine adjustment of the frequency, calculate P1, P2, P3 of PLLA, just write to PLLA P1 / P2 / P3 registers via I2C, no gate/negate operation for clock output, no soft reset for PLLA follows
- Using Msynth for each clocks results the operation latency between operations for each Msynth, it against the regulation between audio clocks
- Using VC-VCXO of Si5351b seems works, but the adjustment range (+-500ppm) is not meet the device spec (+-240ppm), additionally the configuration needs extra DAC for VC input.
- Does the supposed operation work? If no, please let me know your alternatives.
- If yes, please let me know the difference between the existence of soft reset operation after PLLA register operation.
Reprreogramming PLLA is not a good idea. Because everytime you reprogram a PLL, the loop will need to "relock". It will be free running temporarily and can cause output frequencies to drift.
However, there is a much easier way for you to achieve the +/-500 ppm tuning:
1. We have any output OUTx = FVCO/(Nx*Rx), where Rx is a 2^n divider and is usually fixed and does not change but Nx is a fractional multisynth divider.
2. You can reprogram each output OUTx by modifying Nx and Nx can be modified such that you can tune within the +/-500 ppm range.
3. Once you have programmed all the outputs, you can apply a soft reset allowing the outputs to re-align.
The advantage of the above method is that each OUTx change is glitchless and the change is instantaneous. There is no relock time as the VCO frequency is fixed i.e. PLLA is always locked to the input and never changes thereby providing you with operation stability.
Thank you for your support.
Unfortunately, I do not have enough time to check your suggestion.
I'll check your method and report the result on this thread.
I tried your proposed method.
Unfortunately, it does not match my requirement.
When soft reset is executed, just after MultiSynth registers are set for fine adjustment, the output clock re-aligned without considering clock phases at the timing.
So, especially, FCLK phase may drastically change when soft reset executed. It is serious problem for my application.
Without soft reset, this behavior does not occur, but phases between clocks is varied at every iteration of adjustment. It is also bad.
Are there any other ideas for this situation ?
What is the frequency relationship between the output clocks you update ? Are they all the same frequency ?
Please see my first post.
> - Si5351 creates 3 clocks for audio device, master clock (MCLK), bit clock (BCLK), frequency clock (FCLK)
For example, FCLK is 48kHz, BCLK is 64 x FCLK (= 3.072MHz), MCLK is 8 x BCLK (= 24.576MHz).
These three clocks must be phase synchronized because of audio device requirement.
Fine frequency control of these clocks is used to synchronize these clocks with external time stamp.
So, I must make feedback loop to control fine frequency of these three audio clocks.
The fine frequency control is executed during audio working, because the drift between common
time stamp and Si5351 may vary.
Your method with soft-reset results the phase re-alignment between FCLK, BCLK, MCLK without
considering the current phase of these clocks. So, discontinuity must occurs.
My desired operations are:
- Change the fine frequency of FCLK, BCLK, MCLK simultaneously.
- Phase relation between FCLK, BCLK, MCLK must be kept. (e.g. edge of FCLK is match with the edges of BCLK and MCLK)
- Proportion of the frequencies of FCLK, BCLK, MCLK must be kept (1 : 64: 512, for example) even the timing when fine frequency change is executed.
Please let me know the best operation to Si5351.
Can you please send a oscilloscope shot of the "phase error you observe" on multisynth reprogram and soft reset ?
Also, can you confirm that in your programming all clocks have been derived from the same PLL (PLLA and/or PLLB can be used in Si5351).
I attach the oscilloscope shots.
MultiSynth register modification is executed as follows:
Modification for one MultiSynth register set:
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P3_15_08, (tmpP3 >> 8) & 0xFF);
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P3_07_00, tmpP3 & 0xFF);
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_RDIV, SI5351_VAL_MS_OUTPUT_DIV_1 | SI5351_VAL_MS_DIV_BY_NOT_4 | ((tmpP1 >> 16) & 0x3));
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P1_15_08, (tmpP1 >> 8) & 0xFF);
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P1_07_00, tmpP1 & 0xFF);
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P3_P1_19_16,
((tmpP3 >> 12) & 0xF0) + ((tmpP2 >> 16) & 0x0F));
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P2_15_08, (tmpP2 >> 8) & 0xFF);
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_P2_07_00, tmpP2 & 0xFF);
Execute above sequence for three (2, 4, 5) MultiSynth register set.
CLK2 is assigned for MCLK, CLK4 for BCLK, CLK5 for FCLK.
When registers for CLK5, tmpP1, tmpP2, tmpP3 are the same as CLK4. The setting for the register include Output divider is different like follows:
si5351_i2c_write_byte_data(bAddr + SI5351_CTRL_OFST_RDIV, SI5351_VAL_MS_OUTPUT_DIV_64 | SI5351_VAL_MS_DIV_BY_NOT_4 | ((tmpP1 >> 16) & 0x3));
- Because FCLK is BCLK / 64. FCLK is MCLK / (64 * 8), 512 is not supported by divider, so P1, P2, P3 for MCLK, BCLK are individually calculated.
For FCLK, the same P1, P2, P3 as BCLK are used, only Output Divider is different.
All settings are finished, soft reset for PLLA is executed as follows.
si5351_i2c_write_byte_data(SI5351_CTRL_PLL_SOFT_RESET, tmp | 0x20); /* soft reset PLLA */
- The read value is always 0x0C, so I also tried just write 0x2C or 0x20 without reading, but the result is the same.
The result is:
- All clock output stops about 700 usec.
- The recover timing of CLK2 / CLK4 / CLK5 are different.
Description of attached files are follows: (CLK2 (MCLK): Green, CLK4 (BCLK): Pink, CLK5 (FCLK): Blue)
- DS0001.PNG: Clock output stops when soft reset is executed.
- DS0002,PNG: Measure the duration of clock stop (700 usec)
- DS0003.PNG: Recover timing of each clock are not the same timing
Please check and let me know how to operate the register setting for continuous output.
Please remove soft reset at the last step and try again.
If that does not work for you, please raise a technical support ticket. We (silabs) will need to explore if there could be a customized solution that can work for your specific problem.
Thank you for your reply.
As I described the following post, without soft reset, phase alignment is broken.
This situation does not agree with my requirement.
If this works very well in your tests, then use this approach.
Since you only need small skews, the PLL relock time will be shorter than a large step.
You could also experiment with a series of even smaller steps, chained.