There are two ways to control Si5332 output signal enable/disable. One is to configurate register 0xB6 and 0xB7 direclty by I2C. Another is assign GPI to control output with CBPro, but please note that these outputs can't be controled by register 0xB6 and 0xB7 if you have already assigned GPI to control some outputs enable/disable.
Crystal Reliability and Activity Dips
Activity dips can cause disruptions to networking systems and are a regrettable but chronic problem associated with the use of crystals. An activity dip can occur when there are material imperfections in the quartz. These impurities in the crystal structure cause modes of resonance (often called spurs) that are small in amplitude and not located at the fundamental, 3rd overtone, 5th overtone, etc. frequencies.
These resonance modes (or spurs) typically do not cause problems because their amplitude is so much smaller than the amplitude of the fundamental. However, they can have a very large coefficients of frequency vs. temperature. The problem occurs when an oscillator is running at the fundamental and the temperature is changing. In these conditions, the frequency of the spur will be changing much faster than the frequency of the fundamental. If the spur happens to cross over the fundamental, there can be a disruption in the crystal’s oscillation. If the temperature is ramping, this disruption will be temporary because the spur will continue to move and will move away from the fundamental.
The root cause of activity dips is the impurities in the crystal material itself and the probably of having a crystal that is prone to his problem will decrease with better control of the crystal material processing. Crystal manufacturers work very hard to keep the material as clean as possible and therefore the probability of an activity dip is very low. However, it will never go to zero and activity dips are a perennial problem for equipment manufacturers.
What can be done about activity dips? There are three alternatives:
Please note that the embedded crystal versions of the Si537x/8x/9x devices all use solution #3.
For more details on activity dips, see page 57 of the following document:
Accuracy of Phase Noise Measurements With Frequencies Below 100MHz
To ensure the accuracy of the measurements when taking phase noise plots and making RMS jitter measurements, there are times when the instrument being used to take the plots needs to be examined. In particular, the noise floor of the phase noise analyzer (which is typically the Keysight E5052B) needs to be compared to the phase noise being generated by the DUT (device under test). The phase noise of the Si534x/8x/9x devices is so low that in certain circumstances, it is lower than the noise floor of the E5052B.
For a clock that is divided by two by an ideal divider, the phase noise will go down by 6dB. Accordingly, if a phase noise plot of a 2 GHz signal is compared to a phase noise plot of the same signal divided by two, the two plots will look very similar, except that the 1 GHz plots will be 6dB below the 2 GHz plot. With continued divisions by two, the phase noise will go lower and lower until it eventually runs into the noise floor of the E5052B. At this point, the phase noise plot cannot go any lower and the measurement “saturates”. The result will be that the phase noise values will be erroneously reported to be greater than they actually are. The same will be the case for the RMS jitter value because it is derived from the phase noise data.
Though this process is somewhat gradual, it has been our experience that phase noise plots for the Si534x/8x/7x/9x devices with plots below 100 MHz in frequency are affected by the noise floor of the instrument, while phase noise plots for clock frequencies above are typically OK. This is not to say that phase noise plots taken below 100 MHz have no value. Rather the results need to examined in light of these limitations.
For a more detailed discussion of this (and aliasing of higher frequency components down in frequency), see:
If you are encountering the following error when attempting to use the Si5351-EVB，please try the following explanation to fix the issue.
Error Message in CBPro:
error running post frequency plan calculation tasks (step 1); Plan is not realizable please contact Silicon Labs support for further assitance.
This error is usually seen when you configure outputs in three frequency domains and two outputs are greater than112.5MHz.
The general criteria below were used to set the frequency plan in CBPro. This is a general model, and individual applications may require some modification.
1. The Si5351 consists of two PLLs—PLLA and PLLB. Each PLL consists of a Feedback Multisynth used to generate an intermediate VCO frequency in the range of 600 to 900 MHz.
Fout=Fvco/(Multisynth x R)
2. Valid Multisynth divider ratios are 4, 6, 8, and any fractional value between 8 + 1/1,048,575 and 900 + 0/1. This means that if any output is greater than 112.5 MHz (900 MHz/8), then this output frequency sets one of the VCO frequencies.
3. For the frequencies where jitter is a concern make the output Multisynth divide ratio an integer. If possible, make both output and feedback Multisynth ratios integers.
4. Once criteria 2 and 3 are satisfied, try to select as many integer output Multisynth ratios as possible.
OUT1=155.25MHz, OUT2=125MHz and OUT3=94MHz.
CBPro calculates VCO_PLLA=155.25M*4=621MHz and VCO_PLLB=125M*6=750MHz.
But OUT3=94MHz>93.75MHz(750MHz/8), Multisynth divider=750/94=7.9787<8, so the frequency plan cannot be realized.
If OUT3≤93.75MHz, The frequency plan can be realized by Multisynth divider ≥8.
Please see the attached document for Frequently Asked Questions (FAQ) and their answers regarding the Si5372 and Si5371 coherent optical clocks.
The topics from the Table of Contents are listed below.
PCB Design and Layout Guidance
Where should I look for schematic design assistance?
Where can I find the IBIS model for the Si5372/71?
Where can I find the Si5372/71 schematic footprints and symbols?
Do you have layout recommendations I should follow?
Do you have a list of recommended crystals?
I don’t want to use a crystal with the Si5372/71. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device? 2
Are there any power supply filtering requirements or recommendations?
Is there any specific power supply sequencing requirement?
What serial interfaces does the device support?
Are there any power supply filtering requirements or recommendations?
How do I properly terminate input and output clocks?
Where can I get detailed material composition information on these devices?
Is the part RoHS compliant?
What is the Moisture Sensitivity Level (MSL) rating for the Si5372/71?
What is the recommend profile for solder reflow process?
Frequency Plan and Clock Design Decisions
What is the output frequency range of the Si5372/71?
What development software/tools do you have available to use with the Si5372/71?
How do I select proper jitter attenuation bandwidth?
Does the device support automatic input clock selection and does it support hitless switching?
Is there a recommended full device programming procedure?
Can I change one output frequency without disturbing other output(s)?
What is DCO mode and how to use that?
How much power will my frequency plan draw?
How can I know the performance of my frequency plan if I can’t measure phase noise or jitter?
Dose the Si5372/71 support Zero-Delay Mode?
What is the difference between A grade and J grade?
SMBus timeout in I2C timing specification table means
If the SCLK keeps low for longer than timeout.min, the interface will start to reset,
If the SCLK keeps low for longer than timeout.max, the I2C interface will finish the reset.
After the I2C interface reset, customer can restart the talk with our timing products Si534x/7x/8x/9x.
It is better to not have interrupt if you are talking with slave timing products, if not, please make sure the interrupt last time less than 25ms(Timeout.min).
On power up, the outputs will not function as there is no Si5338 programming. So the blank Si5338 outputs will be tri-stated, and the device will be under Loss of Lock and this prevents outputs being driven from Si5338.
After Si5338 is programmed to a configuration, and there is no interrupt event (LOL, LOS or system calibration), the outputs will be driven by Si5338.
If you are encountering the following error when attempting to use either the Si5338-EVB or the Si5338/Si5356 Field Programmer with ClockBuilder Desktop, please try the attached procedure to fix the issue.
DoUSBTransaction: SI_FlushBuffers failed when attempting to reset USB communication. Details: USBXpress error: System error in the operating system. See AN169 for more information on how to get the error information.
When measure differential signal phase noise/jitter performance, an balun must be added to convert differential signal to single end then connect to equipment(eg E5052B). Never connect one of differential signal end to equipment directly, which will has big difference with reality performance.
For example, Si545's real jitter performance of LVPECL 156.25MHz is about 90fs(12KHz~20MHz ). But if you connect one of differential end to E5052B then the test result of jitter is about 250fs.
Please see the attached PDF for the answers to the following questions:
1 What is the main difference between the Si5334, Si5335, and Si5338?
2 Where is the RoHs, REACH, or other material related compliance information for the Si5334, Si5335, and Si5338?
3 Where is the FIT information for the Si5334, Si5335, and Si5338?
4 How can I get a Si5334, Si5335, and Si5338 with a custom startup frequency?
5 What is the default I2C Address of the Si5338 when the part does not have an I2C_LSB pin or a custom address?
6 What finish is used on the contacts of the Si5334, Si5335, or Si5338?
7 How can I burn the NVM on a blank Si5338 part?
8 Will the ClockBuilder Pro Field Programmer (CBPROG-DONGLE) work with the Si5334, Si5335, or Si5338?
9 Where can I find software for the Si5338 Field Programmer?
10 How can I use a CBPro project file with the Field Programmer?
11 Does the Si5338 support in-circuit NVM programming?
12 Can I import a Si5338 ClockBuilder Desktop NVM file into ClockBuilder Pro?
13 How do I control the Si5338-EVB?
14 What if I want a feature in my custom Si5334, Si5335, or Si5338 that is not configurable in ClockBuilder Pro?
15 What is the minimum slew rate for the power supply ramp on Vdd?
16 What power supply sequence/delay is required for Vdd and VDDOx?
17 What should unused VDDOx pins be connected to?
18 When an LOS or LOL occurs, will the outputs be squelched?
19 What do I need to communicate to a Si5338 via I2C?
20 How do I configure a Si5338 via I2C?
21 What is the Input-Output delay of the Si5335 in ZDB and NZDB modes?
22 Can the Si5335/Si5338 clock generators support spread spectrum inputs?
Si53156 is internal termination for maximum integration which the output buffers in Si53156 are push-pull buffers that integrate the 33-ohms series resistance and the 50 ohms to ground. Please refer to AN781 Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x,Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families
For inputs, they are not self-biased. The buffer also expects a DC coupling HCSL input. A bias voltage needs to be provided if the input is AC coupled.
The I2C of Si5332 is compatible with rev6 of the I2C specification, including Standard, Fast, and Fast+ modes. That standard and user manual is here: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
I get a “DUT mismatch error” from CBPro when I plug in the board and start CBPro. This is assuming you’re using an EVB in the default configuration. You’re not wiring from the field programmer board. For details about wiring from the field programmer board please review the user guide. It provides detailed information: https://www.silabs.com/documents/public/user-guides/ug286-clockbuilderpro-dongle.pdf
4. Check Power: USB Power vs External Power: Can you verify several of the test points making sure you're powering from USB? VddA TP1 should be 3.3V. TP2 should be 3.3V, TP23 should be 1.8V. This would verify that the chip is being powered correctly. If you are getting very different numbers this suggests a power problem through the USB path. If there is a problem here could you try powering the board Externally from 5V supply. The procedure to do this is in the user manual that you've been reading. Again, measure the test points.
Silicon Labs has two types of LVPECL drivers for Timing products. Please see below for the recommended LVPECL terminations for these two types of LVPECL drivers.
These LVPECL outputs only support AC coupling but not DC coupling. Customers must use AC coupling for these LVPECL output terminations as shown below:
The termination at the receiver depends on the receiver’s requirements. The only termination requirement from Si534x/7x/8x/9x is seeing an equivalent differential load impedance of 100ohm for signal integrity.
These LVPECL outputs support both DC and AC coupling. Please refer to the below information.
For AC coupling, please note we use different Rb values in different products as shown below:
Recommended Rb value for different Timing products and power supplies
The purpose of this KB is a reminder that different Timing products at Silicon Labs may have different LVPECL structures and therefore different termination requirements. Please refer to the product datasheets, reference manuals and application notes for more detailed termination information when starting designs with Silicon Labs Timing products.
If an input clock is a spread spectrum signal, the spreading function is achieved by adding jitter to the clock. For low loop BW devices, this jitter will be attenuated and effectively removed. A problem that can arise in that there can be false OOF and LOL assertions due to the frequency of the input clock changing over time. This is caused by the dithering of the clock input's spreading function. In order to avoid these false OOF and LOL assertions, the thresholds for OOF and LOL need to be loosened to accommodate the spread.
As an example, consider a 100 MHz spread spectrum clock that has a spectrum spread of ± 5 kHz. Noting that 5 kHz is a change of 50 ppm for a 100 MHz clock, the OOF and LOL assertion thresholds should be set to 50 ppm or greater.
Total Stability for a XO specifies the maximum amount that the XO’s center frequency can drift from its nominal value over all operating conditions, which would typically include temperature stability, initial accuracy, aging for 20 yrs at 70 ºC, load pulling and VDD variation. Supply variation and load variation are less significant factors, typically in the 0.1 ppm range, and these stability factors are often omitted from XO datasheets.
To be short, the total stability can be calculated as:
Total Stability = Initial accuracy + Temp stability (I-temp) + Aging (20 yr 70ºC) + VDD variation + Load pulling.
See the attached file.