Please see the attached document for Frequently Asked Questions (FAQ) and their answers regarding the Si5372 and Si5371 coherent optical clocks.
The topics from the Table of Contents are listed below.
PCB Design and Layout Guidance
Where should I look for schematic design assistance?
Where can I find the IBIS model for the Si5372/71?
Where can I find the Si5372/71 schematic footprints and symbols?
Do you have layout recommendations I should follow?
Do you have a list of recommended crystals?
I don’t want to use a crystal with the Si5372/71. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device? 2
Are there any power supply filtering requirements or recommendations?
Is there any specific power supply sequencing requirement?
What serial interfaces does the device support?
Are there any power supply filtering requirements or recommendations?
How do I properly terminate input and output clocks?
Where can I get detailed material composition information on these devices?
Is the part RoHS compliant?
What is the Moisture Sensitivity Level (MSL) rating for the Si5372/71?
What is the recommend profile for solder reflow process?
Frequency Plan and Clock Design Decisions
What is the output frequency range of the Si5372/71?
What development software/tools do you have available to use with the Si5372/71?
How do I select proper jitter attenuation bandwidth?
Does the device support automatic input clock selection and does it support hitless switching?
Is there a recommended full device programming procedure?
Can I change one output frequency without disturbing other output(s)?
What is DCO mode and how to use that?
How much power will my frequency plan draw?
How can I know the performance of my frequency plan if I can’t measure phase noise or jitter?
Dose the Si5372/71 support Zero-Delay Mode?
What is the difference between A grade and J grade?
SMBus timeout in I2C timing specification table means
If the SCLK keeps low for longer than timeout.min, the interface will start to reset,
If the SCLK keeps low for longer than timeout.max, the I2C interface will finish the reset.
After the I2C interface reset, customer can restart the talk with our timing products Si534x/7x/8x/9x.
It is better to not have interrupt if you are talking with slave timing products, if not, please make sure the interrupt last time less than 25ms(Timeout.min).
On power up, the outputs will not function as there is no Si5338 programming. So the blank Si5338 outputs will be tri-stated, and the device will be under Loss of Lock and this prevents outputs being driven from Si5338.
After Si5338 is programmed to a configuration, and there is no interrupt event (LOL, LOS or system calibration), the outputs will be driven by Si5338.
If you are encountering the following error when attempting to use either the Si5338-EVB or the Si5338/Si5356 Field Programmer with ClockBuilder Desktop, please try the attached procedure to fix the issue.
DoUSBTransaction: SI_FlushBuffers failed when attempting to reset USB communication. Details: USBXpress error: System error in the operating system. See AN169 for more information on how to get the error information.
When measure differential signal phase noise/jitter performance, an balun must be added to convert differential signal to single end then connect to equipment(eg E5052B). Never connect one of differential signal end to equipment directly, which will has big difference with reality performance.
For example, Si545's real jitter performance of LVPECL 156.25MHz is about 90fs(12KHz~20MHz ). But if you connect one of differential end to E5052B then the test result of jitter is about 250fs.
Please see the attached PDF for the answers to the following questions:
1 What is the main difference between the Si5334, Si5335, and Si5338?
2 Where is the RoHs, REACH, or other material related compliance information for the Si5334, Si5335, and Si5338?
3 Where is the FIT information for the Si5334, Si5335, and Si5338?
4 How can I get a Si5334, Si5335, and Si5338 with a custom startup frequency?
5 What is the default I2C Address of the Si5338 when the part does not have an I2C_LSB pin or a custom address?
6 What finish is used on the contacts of the Si5334, Si5335, or Si5338?
7 How can I burn the NVM on a blank Si5338 part?
8 Will the ClockBuilder Pro Field Programmer (CBPROG-DONGLE) work with the Si5334, Si5335, or Si5338?
9 Where can I find software for the Si5338 Field Programmer?
10 How can I use a CBPro project file with the Field Programmer?
11 Does the Si5338 support in-circuit NVM programming?
12 Can I import a Si5338 ClockBuilder Desktop NVM file into ClockBuilder Pro?
13 How do I control the Si5338-EVB?
14 What if I want a feature in my custom Si5334, Si5335, or Si5338 that is not configurable in ClockBuilder Pro?
15 What is the minimum slew rate for the power supply ramp on Vdd?
16 What power supply sequence/delay is required for Vdd and VDDOx?
17 What should unused VDDOx pins be connected to?
18 When an LOS or LOL occurs, will the outputs be squelched?
19 What do I need to communicate to a Si5338 via I2C?
20 How do I configure a Si5338 via I2C?
21 What is the Input-Output delay of the Si5335 in ZDB and NZDB modes?
22 Can the Si5335/Si5338 clock generators support spread spectrum inputs?
Si53156 is internal termination for maximum integration which the output buffers in Si53156 are push-pull buffers that integrate the 33-ohms series resistance and the 50 ohms to ground. Please refer to AN781 Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x,Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families
For inputs, they are not self-biased. The buffer also expects a DC coupling HCSL input. A bias voltage needs to be provided if the input is AC coupled.
The I2C of Si5332 is compatible with rev6 of the I2C specification, including Standard, Fast, and Fast+ modes. That standard and user manual is here: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
I get a “DUT mismatch error” from CBPro when I plug in the board and start CBPro. This is assuming you’re using an EVB in the default configuration. You’re not wiring from the field programmer board. For details about wiring from the field programmer board please review the user guide. It provides detailed information: https://www.silabs.com/documents/public/user-guides/ug286-clockbuilderpro-dongle.pdf
4. Check Power: USB Power vs External Power: Can you verify several of the test points making sure you're powering from USB? VddA TP1 should be 3.3V. TP2 should be 3.3V, TP23 should be 1.8V. This would verify that the chip is being powered correctly. If you are getting very different numbers this suggests a power problem through the USB path. If there is a problem here could you try powering the board Externally from 5V supply. The procedure to do this is in the user manual that you've been reading. Again, measure the test points.
Silicon Labs has two types of LVPECL drivers for Timing products. Please see below for the recommended LVPECL terminations for these two types of LVPECL drivers.
These LVPECL outputs only support AC coupling but not DC coupling. Customers must use AC coupling for these LVPECL output terminations as shown below:
The termination at the receiver depends on the receiver’s requirements. The only termination requirement from Si534x/7x/8x/9x is seeing an equivalent differential load impedance of 100ohm for signal integrity.
These LVPECL outputs support both DC and AC coupling. Please refer to the below information.
For AC coupling, please note we use different Rb values in different products as shown below:
Recommended Rb value for different Timing products and power supplies
The purpose of this KB is a reminder that different Timing products at Silicon Labs may have different LVPECL structures and therefore different termination requirements. Please refer to the product datasheets, reference manuals and application notes for more detailed termination information when starting designs with Silicon Labs Timing products.
If an input clock is a spread spectrum signal, the spreading function is achieved by adding jitter to the clock. For low loop BW devices, this jitter will be attenuated and effectively removed. A problem that can arise in that there can be false OOF and LOL assertions due to the frequency of the input clock changing over time. This is caused by the dithering of the clock input's spreading function. In order to avoid these false OOF and LOL assertions, the thresholds for OOF and LOL need to be loosened to accommodate the spread.
As an example, consider a 100 MHz spread spectrum clock that has a spectrum spread of ± 5 kHz. Noting that 5 kHz is a change of 50 ppm for a 100 MHz clock, the OOF and LOL assertion thresholds should be set to 50 ppm or greater.
Total Stability for a XO specifies the maximum amount that the XO’s center frequency can drift from its nominal value over all operating conditions, which would typically include temperature stability, initial accuracy, aging for 20 yrs at 70 ºC, load pulling and VDD variation. Supply variation and load variation are less significant factors, typically in the 0.1 ppm range, and these stability factors are often omitted from XO datasheets.
To be short, the total stability can be calculated as:
Total Stability = Initial accuracy + Temp stability (I-temp) + Aging (20 yr 70ºC) + VDD variation + Load pulling.
See the attached file.
IO_VDD_SEL bit setting used in the Si534x/8x/9x Customer Evaluation Boards:
The Si539x/8x/4x jitter attenuator timing devices have a power setting IO_VDD_SEL which controls the voltage level to various GPIO pins within the timing chip including the communications pins and status control pins. Please verify with the datasheet for exact pins affected by this power setting.
For systems using a +1.8V host, it is optimal to set IO_VDD_SEL = 0 and all external pullups should be connected to +1.8V. Note that the device GPIO pins are always 3.3V safe regardless of the IO_VDD_SEL setting. The internal GPIO pull-up voltage changes with IO_VDD_SEL (0x0943). It is +1.8V when 0 and +3.3V when 1. In addition to the internal pullup/pulldown, the logic thresholds for the GPIOs are also adjusted by IO_VDD_SEL to give optimum noise immunity at each supply voltage.
The customer evaluation boards (CEVBs) have external pull-ups for these pins set to +3.3V regardless of the IO_VDD_SEL device setting. This is done on the CEVBs because the DUT is always communicating at +3.3V with the MCU for both for SPI/IIC and GPIO inputs and outputs. The DUT should be set to use IO_VDD_SEL = 1, but it will still work when this value is 0. Note that measuring the voltage will always read +3.3V regardless of IO_VDD_SEL. The CEVB MCU has weak software pull ups on the GPIO inputs. Measuring without the CEVB hardware pullups, but with MCU still connected, reads +2.0V when IO_VDD_SEL = 0. Disconnecting the MCU jumper resistor as well as the external pullups gives the correct device value of +1.8V when IO_VDD_SEL = 0. This
Please refer to the datasheet to ensure which pins are affected by the IO_VDD_SEL setting and follow all the datasheet and reference manual recommendations.
Si538x/4x/9x General Troubleshooting Guidelines: I’ve set up my timing chip but I do not see an output
1. Make sure there is power to each of the VDDOs. If using a Silicon Labs EVB this means you can go to the EVB GUI of CBPro to the Regulators Tab and make sure the regulators are all turned on. Or you can turn them on and keep them always on using the jumper pins on the EVB located near each of the outputs. See KB Article about EVB Outputs for the Si534x/9x/8x https://www.silabs.com/community/timing/knowledge-base.entry.html/2018/11/08/si534x_9x_8x_evbout-HMKe
2. Check the OEb pin on the chip. The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high all outputs will be disabled. When the pin is not driven, the device defaults to all outputs on. The OEb pins have an internal pull down. For the Si5397 and Si5347 devices when using the OE1b it is recommended to use an external pull down to ensure the outputs are on, or a pull up to ensure they are off and not leave this pin floating. The OE0b pin has an internal pull down, but this OE1b pin does not in this case only. Outputs in the enabled state can be individually disabled through register control. Please NOTE: If the OEb pin is high, then register control is disabled, and all outputs will be disabled.
3. Check the OUTx_PDN Registers and make sure they are NOT powered down. Also check OUT_PDN_ALL, and PDN. These are all documented in the reference manuals for the specific parts.
4. Check the Output Enable Registers (OUTx_OE). Verify that the outputs are enabled . Also make sure OUTALL_DISABLE_LOW is set high, ensuring all outputs are not disabled. This is a register to disable all outputs by clearing this bit.
5. Connect to CBPro and read the EVB GUI status registers? An output may not appear if something is wrong with the XAXB input. Verify there is no XAXB Error. If there is an Error, check the input going to the XAXB. This may be what is causing the issue.
6. Is the chip programmed correctly? Verify some registers that were written from the frequency plan on different pages to make sure there wasn’t an issue with programming the chip. See AN926 for detailed examples on how to program these devices. It is possible the device was not programmed correctly which is causing the problem. https://www.silabs.com/documents/public/application-notes/an926-reading-writing-registers-spi-i2c.pdf
Si534x/9x/8x General Troubleshooting Guidelines: My timing device does not lock
This is a common question for jitter attenuator timing devices. One thinks the device is configured properly. The chip was programmed for the correct frequency plan file/ register set and it should just lock and work, but there is indication that the device is not locked either from the LOL alarm status or because downstream systems are failing. The following are some helpful troubleshooting steps to consider particularly for the Si534x/9x/8x jitter attenuator devices.
1. Verify the hardware is set up correctly: Do a quick schematic review, following the checklist: https://www.silabs.com/documents/public/application-notes/AN1051-Si534x-8x-Schematic_Review-Checklist.pdf
Make sure the expected inputs are on, measured and are the correct frequency. Make sure to use proper terminations and input levels and rise time considerations. Make sure the correct source is used on the XAXB input and programmed accordingly to the correct expected frequency. Make sure the correct communications are enabled (either I2C/SPI). Also double check that the frequency plan matches the hardware setup, such that programmed input frequencies, and XAXB input frequency correctly matches the hardware.
2. Verify the alarms: What alarms are active when the device does not lock? Please review the appropriate reference manual to find the register values for these alarms and check the status.
LOL: This is the indicator that the device is not locked. This is the issue you are debugging. This should be set showing the device is not locked. Let’s find out why!
SYSINCAL: This shows at start up the device is stuck in calibration. This indicates that device is busy in the calibration routine. This might be that the chip is improperly set up, programmed incorrectly or has the wrong xaxb input frequency if this alarm remains set.
LOSXAXB: This shows that the PLL is not seeing the XAXB input signal. Is the XTAL soldered properly to the board to the XAXB input pins? If using an XO is it turned on, connected and has the proper input constraints per the datasheet?
XAXB_ERR: There is a problem locking to the XAXB input. This indicates that the part may be programmed to the wrong frequency or the XAXB input may be different from what you were expecting, or there is a violation of the input specifications. Verify all input datasheet specs, the programmed frequency and measure the frequency going into XAXB.
OOF: This flag indicates that the input is outside the set threshold frequency range. You can widen the OOF threshold limits to see how far off the input signal is.
LOS: This is the loss of signal flag indicating that the input does not see an input signal. Please check that the input is connected to the expected input and all datasheet parameters are met.
3. Which input is the device expecting to lock to? Check register IN_ACTV. This is a read only register which give the current selected DSPLL input clock. For the Si5345 this is register 0x0507 as there is only one PLL. For multi PLL devices make sure to verify which PLL the loop is configured to. In multi PLL devices these will be labeled IN_PLLA_ACTV, IN_PLLB_ACTV, IN_PLLC_ACTV, IN_PLLD_ACTV.
4. Verify the input control settings: If pin controlled, then check the pin settings. If register controlled then check IN_SEL. If using a device with Zero Delay mode enabled verify with the reference manual for the input selection details. When this function is enabled the inputs can be register controlled with ZDM_IN_SEL.
5. Verify the device was programmed correctly: The Si534/8x devices have 2-byte wide register addresses but the device is only 1-byte programmable. The upper byte of the address is stored as the PAGE register which is always address 0x01. This often confuses customers. Please review AN926 for details on reading and writing registers with SPI and I2C. This document contains examples on how to properly communicate to the part. https://www.silabs.com/documents/public/application-notes/an926-reading-writing-registers-spi-i2c.pdf . It is also good to do a few sanity checks that the device was programmed correctly by reading back several of the registers written to the device, on different pages.
I have one of the Silicon Labs Timing Jitter Attenuator/Clock Generator Si534x/8x/9x evaluation board boards that uses CBPro and I cannot see an output signal after configuring my plan.
The CBPro software has a configuration wizard to help customers create their frequency plan, informing the customer of all the decisions they need to make to optimize all the settings. CBPro also has an EVB GUI which allows the user to do some debug, control the output regulators and view status alarms while the device is running. If the outputs are not turning on it is most likely that the output voltage regulators are not on. To check this, go to the EVB GUI and click on the Regulators tab and turn on the output regulators. They are operable independently.
One can also control the output regulators from the EVB so the PC is not required to turn on the regulators. There is an Enable jumper that can be installed for each of the outputs. When the jumper is set this enables the output. Then there is another jumper that can be installed to select between 1.8V, 2.5V and 3.3V. Attached is an image of a Si5394 EVB pointing to the output driver jumper area for output 1.