Accuracy of Phase Noise Measurements With Frequencies Below 100MHz
To ensure the accuracy of the measurements when taking phase noise plots and making RMS jitter measurements, there are times when the instrument being used to take the plots needs to be examined. In particular, the noise floor of the phase noise analyzer (which is typically the Keysight E5052B) needs to be compared to the phase noise being generated by the DUT (device under test). The phase noise of the Si534x/8x/9x devices is so low that in certain circumstances, it is lower than the noise floor of the E5052B.
For a clock that is divided by two by an ideal divider, the phase noise will go down by 6dB. Accordingly, if a phase noise plot of a 2 GHz signal is compared to a phase noise plot of the same signal divided by two, the two plots will look very similar, except that the 1 GHz plots will be 6dB below the 2 GHz plot. With continued divisions by two, the phase noise will go lower and lower until it eventually runs into the noise floor of the E5052B. At this point, the phase noise plot cannot go any lower and the measurement “saturates”. The result will be that the phase noise values will be erroneously reported to be greater than they actually are. The same will be the case for the RMS jitter value because it is derived from the phase noise data.
Though this process is somewhat gradual, it has been our experience that phase noise plots for the Si534x/8x/7x/9x devices with plots below 100 MHz in frequency are affected by the noise floor of the instrument, while phase noise plots for clock frequencies above are typically OK. This is not to say that phase noise plots taken below 100 MHz have no value. Rather the results need to examined in light of these limitations.
For a more detailed discussion of this (and aliasing of higher frequency components down in frequency), see: