What is the required load impedance for the EZRadio Si422x transmiter device in order to achieve maximum output power? Is it the complex conjugate match or something else?
For the TX chip the load impedance required for the maximum output power is not the load impedance for conjugate complex matching but the impedance which (together with the output impedance of the chip) maintains the maximum available voltage swing at the RF output.
These values can be found in the Datasheets.
I use the suggested matching balun network for the EZRadio® chips but still the output power to 50 Ohm is lower than in the Datasheet. What could be the problem?
The problem could be the incorrect layout design. We have reference designs for the layouts of the matching baluns; the recommended component values are valid only with those layouts.
With different matching network layout design the parasitic (usually additional inductances due to the increased distance between the SMD components and the long thin traces between them) can detune the balun. We recommend using the reference layout design.
Another problem could be the component Q. If the reference layout is used then it is very likely that the output power is lower due to the lower inductor Q or different parasitic of the SMD components.
See also the recommended SMD component properties.
Why is there a “6 dB” output power limitation in the older 0.5 mm thick PCB reference designs using the 434 MHz cross-tapped loop antennas (see Antenna Selection Guides) for the Si4021 and Si4421?
For both, there is a “6dB” output power limitation due to the antennas parallel resistance, which is larger than the optimal required load resistance (for maximum output power).
At the Pmax output power state the RF output becomes saturated due to the limited voltage swing. In a proper and reduced output power state, the RF current is lowered so the output is not in saturation, here there is a decrease in the radiated power but he range decrease is not substantial (under 10%). In addition, the reduced output power state provides a lower current consumption and reduced harmonics.
What happens if the output of a transmitter is open circuited during operation?
An open circuited transmitter output can malfunction after a short period of operation.
The reason is that the tail current generator of the output differential driver pair forces the output transistor into saturation and the emitter base diode opens. This high DC current (~12mA) is then forced to flow to the preceding emitter follower output stage, and from this point it becomes unpredictable, where it may become damaged.
Do baluns have to be used to interface with a cross-tapped loop antenna for Si4010/Si4012?
The cross-tapped loop antennas are high impedance differential antennas.
Their impedance is adjusted to be close to the optimum differential antenna impedance and as such the antenna can be connected directly to the chip outputs. One caveat however is that the antenna needs to be connected exactly to the input points of the antenna as a transmission line will detune the impedance and degrade the radiation.
Do loop antennas require a ground plane?
Loop antennas do not require any ground plane, and actually perform slightly better without one.
In reality however, as the rest of the application circuitry is positioned beside the antenna the antenna properties are effected by this proximity in terms of impedance and radiation properties. To reduce the effects of the application circuit it is recommended to fill the gaps with ground metal, this in turn effectively becomes a small ground plane.
What are the recommended values of the Vdd filter capacitors for the EZRadio® products (and why)? Is there any recommendation for their position?
The proper Vdd filtering is essential to avoid unwanted spurs.
1. Filtering is necessary at the fundamental RF frequency. The value of this capacitor depends on the operation band, e.g.:
~33pF at 915MHz, 47pF at 868MHz, 220pF at 434MHz and ~330pF at 315MHz with 0603 size SMD capacitors (MURATA GRM18);
~56pF at 915MHz, 68pF at 868MHz, 270pF at 434MHz and ~470pF at 315MHz with 0402 size SMD capacitors (MURATA GRM15).
Component value selection is based on the goal that the capacitor's SRF, self resonance frequency, must fall onto the RF fundamental frequency. These will ensure having good RF filtering by applying a notch filter to the GND.
It is very important that this capacitor should be placed as close to the VDD pin of the EZRadio® chip as possible, connected with wide, short leads (to minimize the series parasitic inductance of the lead). The other side of the capacitor has to be soldered to a very good RF ground point (good RF ground means that it is equipotential with the GND pin of the chip i.e. wide short connection or large ground metal with stitching vias).
2. Filtering necessary at the crystal frequency and at its harmonics (first few harmonics). If these clock harmonics are on the Vdd they are up converted by the internal VCO and appearing as n x Xtal_freq side spurs around the carrier. Causing harmful radiation and thus failing in ETSI or FCC compliance testing.
For this filtering capacitors with value of ~10nF are the best (again use the GRM18 type as reference). This capacitor can be a little away from the Vdd pin of the EZRadio® chip as the filtered frequency is lower but still put it as close as possible.
3. Filtering of the 1MHz...10MHz clock signal to the uC: pin 8 (Si4x3x) is a clock output buffer to supply clock for microcontrollers. Its frequency can be varied between 1MHz and 10MHz (the default is 1MHz). Especially if this buffer is on this clock may appear on the Vdd pin of the chip and causing problems. To avoid this capacitor with several uF is necessary. In our tests a 2.2uF ceramic SMD capacitor (GRM18) was the best, but a tantalum is good as well even with bigger sizes. The value can go up to 10uF and can be placed farther from the chip pin than the lower-valued capacitors mentioned in the above points.