If the LDETB signal cannot be used as a PLL settling indicator, what approach should one take?
As noted in RF Synthesizer Knowledge Base article LDETB signal as PLL settling indicator (90292), the LDETB signal should not be solely relied on as a PLL settling indicator. This is because it also serves to indicate the PLL is about to lose lock due to temperature drift. Therefore LDETB can be asserted before the PLL has sufficiently settled in an application, e.g. to within 0.1 ppm of the settled final frequency.
The best approach is to allow for the maximum settling time and then check LDETB. The Si4133 datasheet (Rev. 1.61 as of this writing) for example gives the following guidance regarding settling time:
The settling time for the PLL is directly proportional to its phase detector update period TΦ (TΦ equals 1/fΦ). A typical transient response is shown in Figure 6 on page 11. During the first 13 update periods the Si4133 executes the self-tuning algorithm. From then on the PLL controls the output frequency. Because of the unique architecture of the Si4133 PLLs, the time required to settle the output frequency to 0.1 ppm error is automatically 25 update periods. The total time after powerup or a change in programmed frequency until the synthesized frequency is settled—including time for self-tuning—is approximately 40 update periods.
Note: The settling time analysis holds for RF1 fΦ > 500 kHz.
Testing should be employed to confirm the worst case settling time for the worst case update rate in any particular application.