What HVRAM locations of the Si4010 are used by the API?
There are two API functions that write the HVRAM (beside vHvram_Write): 1. vSys_FirstPowerUp a. Clears the HVRAM. b. Initializes the HVRAM byte at address 0x02 to 0xFF. It happens only when battery was inserted, so this location can be used by the user code for any purpose. 2. vSys_Shutdown Clears bit in HVRAM which means "chip didn't shut down correctly."(bit 0 at address 0x00) If user wants to use this bit to check if shutdown was called, it has to be set by user code.
Conclusion: The whole HVRAM except the first bit can be used freely by the user code.
The Si4010 MTP counter examples show how to set up for between 20-bits and 32-bits. Can the user set this up for 16-bits?
The '20bit to 32bit' references the overall balanced counter width, which is needed to store the counter value in MTP memory. These balanced counters can count up to 550k-1040k. The MTP API module does not implement a 16 bit counter.
However, by using a normal 16bit counter without any Gray coding, counting up to 50k is possible. 50k is the guaranteed minimum endurance of the MTP memory bits, first reached on LSB in this case. It is therefore possible to count up to at least 50000 by incrementing and storing a two byte variable in MTP memory, without an API to encode/decode.
Sometimes a continuous standard preamble comes in handy for testing purposes.
With RevC2A chips it is possible to internally modulate with an infinite square wave pattern. Basically, we use the PN9 modulation mode but load up a ‘1010…’ seed pattern into the LFSR and then just circulate it forever.
(There was a bug in RevB1B chips that prevented this from working directly)
The following batch lines can be added to the end of a WDS generated CW batch:
(Remember to remove the original MODEM_MOD_TYPE setting)
# Set PN polynomial = 16-bit circulator
'SET_PROPERTY' 'PKT_WHT_POLY_15_8' 80
'SET_PROPERTY' 'PKT_WHT_POLY_7_0' 00
# Set PN Polynomial seed value = 0xAAAA (1010... pattern)
'SET_PROPERTY' 'PKT_WHT_SEED_15_8' AA
'SET_PROPERTY' 'PKT_WHT_SEED_7_0' AA
# Switch to PN9 mode (must be set after polynomial & seed)
The Si4010 datasheet states that the Roff option can be used to disable internal pull-up on GPIO1 and GPIO2, and external pull-up can be used. Is there a recommended maximum value of this external pull-up?
What is the resolution of the RX FIFO Almost Full interrupt on C2A revision of the EZRadioPRO radios?
The resolution is four bytes. This means that if the RX FIFO Almost Full threshold (PKT_RX_THRESHOLD) is set to 1, 2, 3 or 4 bytes, the RX Fifo Almost Full interrupt arrives after the reception of the fourth byte of the payload, plus about 30-60µs delay.
If the threshold is 5,6,7 or 8 bytes, the interrupt arrives after the 8th byte, e.t.c.
Will a code written for RevB1B be running on RevC2A?
Yes, RevC2A is backward compatible with RevB1B. That is to say a code that was originally developed for a RevB1B chip, should be running on a RevC2A chip without any modification. Note, however, that if the RevC2A chip is using a feature that needs a patch (e.g. Patch ID 0x311A), the power-up sequence has to be slightly different, meaning that the host firmware has to be upgraded. Commands and properties that existed on RevB1B did not change on RevC2A, therefore the radio configuration does not have to change.
The reverse is not true, however. Since there are new commands and properties on RevC2A, a code written for RevC2A may not run on RevB1B.
Both the Si4460/61/63 Rev C2A and Si4467/68 RevA2A chips can be configured to transmit and receive 802.15.4g compliant packets. The PHY layer of the standard is supported by HW. That includes CRC calculation (both 16- and 32-bit), data whitening, modulation type (2GFSK, 4GFSK), all sub-GHz frequency bands, PHR parsing (i.e. processing the packet header at the RX side in order to receive the right amount of bytes, select CRC type, enable/disable data whitening). There is an 802.15.4g bidirectional example project available under WDS, which is documented in AN633. Note that the MAC has to be implemented by the host MCU code, it is only the PHY that is supported by hardware.
PART_INFO and FUNC_INFO API commands can be used for that purpose. For example, a Rev B1B chip corresponds to ROMID 3 (see PART_INFO), chip FW ID 3.0.15 (see FUNC_INFO:
REV_EXT, REV_BRANCH, REV_INT). A Rev C2A chip corresponds to ROMID 6, FW ID 6.0.2, and a Rev A2A chip corresponds to ROMID 6, FW ID 6.0.7. If a patch is applied, it will be returned by FUNC_INFO. For example, Rev C2A has a published patch automatically being downloaded from within WDS, therefore FUNC_INFO will return Patch ID 0x311A.
Can the length of the Sync Word be defined as an arbitrary number of bits?
With Si443x chips or Si446x Rev B1 chips, the answer is: no, the length of the Sync Word must be defined in number of bytes (1 to 4 bytes in length).
With Si446x Rev C chips, the answer is: yes (almost). It is possible to configure Si446x_RevC chips for a Sync Word length that is an even number of bits, but it is not possible to configure the length to an odd number of bits.
This configuration is obtained by first "rounding up" the desired number of bits to next-highest byte count, and setting the SYNC_CONFIG:LENGTH API property to the appropriate enumeration. Example: if a Sync Word length of 14 bits is desired, this would be rounded up to 16 bits = 2 bytes, and the SYNC_CONFIG:LENGTH property field would be set to enumeration LENGTH = 1. The SYNC_CONFIG2:LENGTH_SUB property field would then be used to "subtract" an even number of bits from this defined length. Continuing this example of a desired length of 14 bits, it would be necessary to subtract 2 bits from the Sync Word length and thus the SYNC_CONFIG2:LENGTH_SUB property field would be set to enumeration LENGTH_SUB = 1.
However, it is always possible to "steal" an odd number of bits from the preceding Preamble field. For example, if a 13-bit Sync Word length is desired, the chip could be configured for a 2-byte = 16-bit Sync Word length. The desired 13-bit Sync Word value would be packed into the lower 13-bits of this 2-byte Sync Word definition, with the upper three bits defined as '010' or '101' (i.e., the tail end of the Preamble field just prior to the start of the Sync Word).
It is not possible to define a Sync Word length of zero bytes or bits. This has no meaning; it is not possible to find a bit pattern with a length of zero bits. However, it is possible to configure the chip to not care if a Sync Word is detected or not. This is accomplished by setting the PREAMBLE_CONFIG_STD_1KIP_SYNC_TIMEOUT bit.