For the SPI settings, you can refer to section 3.6 <spi> in the <<Configuration Guide>> doc. The "divisor" parameter is used to set the SPI clock frequency for master mode.
The internal clock PBCLK provided to the SPI module is a divider function of the CPU core clock (see below equation). This clock is divided based on the value of "divisor" parameter. The SCKx clock obtained by dividing PBCLK is of 50% duty cycle and it is provided to the external devices via the SCKx pin.
Below equation shows how to calculate the clock frequency and there are examples for your reference.