When designing an EZSP-based solution with the EM351 or EM357 network coprocessor [NCP], it is useful to know the configuration of the individual GPIO pins, whether to ensure proper signal logic between the host and NCP or to optimize current draw on the board while in various modes of operation. Since Ember’s EM35x reference designs generally describe only the necessary SPI/UART signals necessary for EZSP connection between the host and NCP, additional information about the EM35x chip’s GPIO configuration in NCP firmware can be helpful in determining the direction/logic employed for unused pins so that these unused pins can be tied to appropriate logic to prevent unwanted current draw.
The list below provides descriptions of all of 24 GPIO pins and their GPIO configuration in the EZSP-SPI firmware (which is preferred over EZSP-UART when current consumption is a concern since NCP deep sleep operation is not yet supported in EZSP-UART). This should allow hardware and firmware designers to determine the appropriate connection for pins they aren’t using. (It’s good to tie even the input pins to a known state [VCC or GND] to ensure a consistent operation from the chip and handle some of the unusual operational states like during reset or during bootloading, but if you had to leave these floating, it probably wouldn’t be a big impact to your overall current consumption.)
Additionally, a few GPIOs are relied upon by the SPI bootloader firmware used on EZSP-SPI NCP devices while in boot mode:
If you have additional questions or concerns about these pin assignments or I/O functions, please contact Silicon Labs support.