When designing an EZSP-based solution with the EM351 or EM357 network coprocessor [NCP], it is useful to know the configuration of the individual GPIO pins, whether to ensure proper signal logic between the host and NCP or to optimize current draw on the board while in various modes of operation. Since Ember’s EM35x reference designs generally describe only the necessary SPI/UART signals necessary for EZSP connection between the host and NCP, additional information about the EM35x chip’s GPIO configuration in NCP firmware can be helpful in determining the direction/logic employed for unused pins so that these unused pins can be tied to appropriate logic to prevent unwanted current draw.

The list below provides descriptions of all of 24 GPIO pins and their GPIO configuration in the EZSP-SPI firmware (which is preferred over EZSP-UART when current consumption is a concern since NCP deep sleep operation is not yet supported in EZSP-UART). This should allow hardware and firmware designers to determine the appropriate connection for pins they aren’t using. (It’s good to tie even the input pins to a known state [VCC or GND] to ensure a consistent operation from the chip and handle some of the unusual operational states like during reset or during bootloading, but if you had to leave these floating, it probably wouldn’t be a big impact to your overall current consumption.)

• PA0 – MOSI (floating input from SPI host; configured as input/pull-up in deep sleep)
• PA1 – MISO (alt. output from SPI host; configured as input/pull-up in deep sleep)
• PA2 – SCLK (floating input from SPI host; configured as input/pull-up in deep sleep)
• PA3 – nSSEL / IRQC (input/pull-up from SPI-host; configured as input/pull-up in deep sleep)
• PA4 – PTI_EN (alt. output modulated by PacketTrace Interace [PTI] on InSight Port; configured as input/pull-up in deep sleep)
• PA5 – PTI_DATA (alt. output modulated by PacketTrace Interace [PTI] on InSight Port; configured as input/pull-down in deep sleep)
• PA6 – LED (output used to indicate TX/RX activity from stack software; defaults to off LED off / high; configured as output/high in deep sleep)
• PA7 – Unused in EZSP (unused output; always left high / off; configured as output/high in deep sleep)
• PB0 – Unused in EZSP (unused output; always left high; configured as output/high in deep sleep)
• PB1 – TXD (alternate output to UART host; configured as input/pull-up in deep sleep)
• PB2 – nHOST_INT / RXD (active-low output to SPI host or input from UART host; configured as input/pull-up in deep sleep)
• PB3 – nSSEL_INT / CTS (active-low input from SPI or UART host; configured as input/pull-up in deep sleep)
• PB4 – RTS (alt. output to UART host; configured as input/pull-up in deep sleep)
• PB5 – Unused in EZSP (unused input; always pulled down; configured as input/pull-down in deep sleep)
• PB6 – nWAKE / IRQB (active low input from SPI host; always pulled up; configured as input/pull-up in deep sleep)
• PB7 – Unused in EZSP (unused alt. output; always low; configured as input/pull-down in deep sleep)
• PC0 – JRST (alt. output to debugger; configured as input/pull-up in deep sleep)
• PC1 – Unused in EZSP (unused output; always low; configured as output/low in deep sleep)
• PC2 – JTDO / SWO (alt. output to debugger; configured as output/high in deep sleep)
• PC3 – JTDI (input from debugger; configured as input/pull-down in deep sleep)
• PC4 – JTMS / SWDIO (input from debugger; configured as input/pull-down in deep sleep)
• PC5 – TX_ACTIVE (alt. output for optional PA/FEM; goes high while radio is in TX mode; configured as output/low in deep sleep)
• PC6 – nTX_ACTIVE (alt. output for optional LNA/FEM; goes low while radio is in TX mode; configured as output/low in deep sleep)
• PC7 – Unused in EZSP (unused output; always low; configured as output/low in deep sleep)

Additionally, a few GPIOs are relied upon by the SPI bootloader firmware used on EZSP-SPI NCP devices while in boot mode:

• PC6 – The PC5 and PC6 pins are utilized for TX_ACTIVE and nTX_ACTIVE as above.
• PA6 and PA7 are used as LEDs (active-low outputs) to indicate bootloader progress. PA6 will be on/low while bootloader is idling in normal operation (before and after the transfer) and will toggle repeatedly while the firmware download is occurring. PA7 will be toggle repeatedly while waiting for the download to begin and will go off/high when the download does begin.
• The 7 EZSP-SPI connections between the host/NCP behave in their default EZSP-SPI configurations as above, but with the following caveat…
• PB6/nWAKE serves as the trigger pin to force bootloader activation through hardware as an alternative to launching the bootloader via the host’s ezspLaunchStandaloneBootloader() command. It is configured as input/pull-down during the boot sequence and sampled by the bootloader startup code; if it is found to be held low externally, the SPI bootloader is launched instead of the normal EZSP firmware.

If you have additional questions or concerns about these pin assignments or I/O functions, please contact Silicon Labs support.