We offer the broadest portfolio of ultra-low jitter timing solutions, addressing reference clock requirements in all aspects of data center hardware design. We focus on simplifying clock tree design, offering frequency flexible, highly integrated solutions capable of being customized to each individual set of reference clocks requirements using our ClockBuilder Pro software.
Data center hardware architecture is evolving to meet increased workloads through networking bandwidth upgrades, increases in data rates, application optimized data processing, and addition of IEEE 1588 precision time protocol. Our partnerships with processor, FPGA, and PHY, and SoC suppliers, as well as involvement in the PCI-SIG, drive our specifications and roadmap to ensure our products provide a significant amount of design margin to next-generation platform reference clock requirements.
PCIe-Express is the primary data bus interconnect used throughout the data center. Switches, servers, smartNICs, accelerator cards, SSDs, and flash array storage designs are now being deployed with Gen4 capabilities, and will soon adopt the recently ratified Gen5 standard. As an active PCI-SIG working group member, our system architects are making significant contributions to existing and future generations of PCIe reference clock specifications and overall system jitter budgets. PCIe reference clock specifications include specific RMS phase jitter filter masks for each generation of the standard, which are usually not available in commonly used oscilloscope and spectrum analyzers. To simplify the process and ensure accurate measurements, Silicon Labs developed a comprehensive desktop software tool that has quickly become the industry standard in PCIe reference clock jitter measurements.