Microprocessor controlled devices provide virtually any frequency translation combination across this operating range. For ease of use, pin-controlled devices are preconfigured to support popular SONET/SDH, Ethernet, Fibre channel and HDTV frequencies. The any-rate precision clocks are based on Silicon Labs'third-generation DSPLL® technology, which provides any-rate frequency synthesis and 300 fs RMS typ jitter performance in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.
The Si53xx is the industry's first jitter attenuating clock multiplier IC that provides any-rate frequency synthesis. With jitter performance of 0.3 psRMS typ, the Si53xx rivals the best jitter performance available using discrete analog PLL technology.
The highly integrated Si53xx contains all the key components of a high-performance analog PLL on chip, including an ultra-low phase noise voltage-controlled oscillator (VCO), loop filter, phase detector, divider and buffers. Because all PLL components are integrated, board-level noise immunity is improved versus discrete solutions. With up to four clock inputs and five differential clock outputs available, the Si53xx eliminates the need for external muxes and clock distribution buffers, further reducing BOM part count and cost.
The Si53xx frequency plan is easily reconfigurable using pins or an I2C/SPI interface, simplifying design reuse. The Si53xx integrates system-level clock features including hitless switching, automatic (revertive, nonrevertive) clock control, holdover, selectable output clock signal formats and programmable output clock phase control.
Silicon Labs’ proprietary DSPLL technology uses digital signal processing (DSP) techniques to move traditionally analog PLL functions into the digital domain. The Si53xx integrates a high performance, low phase noise VCO, loop filter, phase detector, dividers, input clock selection mux, and flexible output buffers on-chip, replacing discrete analog PLL implementations.
The DSPLL loop bandwidth is digitally programmable from 4 Hz to 1.6 MHz, providing jitter performance optimization at the application level. Devices are offered in two package options: a 6 x 6 mm 36-pin QFN for devices with one or two clock outputs and a 14 x 14 mm 100-pin TQFP for products with five clock outputs. Given their frequency flexibility and outstanding jitter performance, Silicon Labs any-rate precision clocks are ideal for providing clock multiplication, jitter attenuation and clock distribution in high-performance timing applications.