In a post in the 'annoucements' forum, Tabitha asks, 'Have an Application Note idea?'
Not an idea, but perhaps some clarity. Section 3 of the Si514 data sheet is 'All-digital PLL applications,' and it refers to AN575: An Introduction to FPGA-Based ADPLLs.
The app note is pretty good, except for one thing: the source code isn't available. I opened a support request back in May 2012 to get that code, and was told, 'Unfortunately, the Verilog source code for that ADPLL is not ready for release, and we don't have the time or resources at present to finalize and support it.' I followed up by saying that I didn't need support, really, just to see what they were thinking. The final follow-up was that the code wasn't being released at that time.
So is there any way, 18 months later, to kick out that code, even if it's not ready for prime time?
I'm playing with an ADPLL concept based on the Si514 and I'm looking for ideas.
Anyone can please help me in defining how to measure a mid-level voltage (Vo). This voltage is used in LVDS output section of Si570, Si534, etc and I am not sure what must be the exact measurement points for measuring this type of parameter.
Please give your valuable suggestions.
What does total stability of the SI530 encompass?
Does it include affects due to voltage, temperature initial turn on and aging?
I need to determine the total frequency drift over 20 years.
As an external reference for chip Si5324D-C-GM used 40 MHz quartz (frequency tolerance 30 ppm or 3E-5). Frequency input of the chip is connected to the generator (10 MHz, stability 5E-11).
What is stability of the output clock of the chip (near 5E-11 or much lower)?
About oscilator 531 series
Please tell me the value minimum/typical value of Rise/Fall time (20/80%).
I am currently planning to use using one Si5374 and two Si5326 Clock multipliers together for a custom designed board. All three clock multipliers will be referenced to a common 10 MHz clock and a common 122.28MHz crystal reference using zero-delay fan-out buffers. I am plan to generate a nominal 250MHz clock output from all clock multipliers.
My question is related to the clock phase-sync within the clock multiplier outputs and between all three clock multipliers. By phase-sync, i mean that i expect the 250 MHz clock outputs (all 12 outputs) to have the same/constant phase relation with respect to each other after every power-up/ reset/ spi-ical programming, without phase 0/90/180 degree phase ambiguities.
Are the two outputs from Si5326 always phase-synced by design ?
Are the two outputs from a single DSPLL core of Si5374 phase-synced by design ?
Are the eight outputs from the four DSPLL cores within Si5374 phase-synced by design ?
Is it possible to have all 12 clock outputs (8 from Si5374 and 2 each from Si5326) phase-synced ?
Why go to all the expense of using a crystal oscillator when it seems just as good as to bolt a crystal alongside any IC to clock it?
I am working on a project which needs the RF Board to be synchronized with the FPGA.
The FPGA is being driven by a 10 MHz clock. Is there a way to configure the SI5336 in NUAND RF Board to output 10 MHz clock or
fed in 10 MHz clock from an external source ?
I tried changing the following register values for getting clock out from the RF board.
Can the Si53340 be used as a generic data buffer, rather than as a clock buffer? I see it has AC specs down to DC (i.e. not stopping at 1 MHz Min F like the 5330x.) Its Any In - Any Out structure would be handy if so as a translator.
sorry my english
in Si53xxReferenceManual.pdf written "See DSPLLsim for a table of BWSEL_REG and associated loop bandwidth settings"
but, i my software driver calculates the parameters and upload the settings to the chip. And i am want correct calculate BWSEL
How calculate possible BWSEL ?
I'm in design phase of a new board.
I need to generate a low-jitter (<10ps rms) 26MHz CMOS clock, from 100MHz clock (levels of input clock are flexible).
Input clock may have 15ps rms jitter, 150ps PkPk.
I was looking at Si5319, and it seems to be good for the job.
I used to software from Silabs to calculate the required registers values.
1. Will the phase of the output clock will be the same on every power-up (relative to input clock) ?
2. Is it possible to get pre-programmed samples with my required config, that will not need I2S/SPI config on each power-up ?
3. What kind of jitter I can expect on the output clock based on the above data ?