Please see the attached PDF for the answers to the following questions:
Please see the attached PDF document below for the answers to the following questions:
1 Where is the RoHs, REACH, or other material related compliance information for the Si5350 or the Si5351?
2 Where is the FIT information for the Si5350 or the Si5351?
3 What are the Tape & Reel Specs for the Si5350/51?
4 How can I get a Si5350 or Si5351 with a custom startup frequency?
5 What is the default I2C Address of the Si5351 when the part does not have an A0 pin?
6 What finish is used on the contacts of the Si5350 or the Si5351?
7 How can I burn the NVM on a blank Si5351 part?
8 What if I want a feature in my custom Si5350 or Si5351 that is not configurable in ClockBuilder Pro?
9 Can a CMOS clock be driven into the XA or XB pins of the Si5350 or Si5351?
10 What is the output-to-output skew of the Multisynth outputs?
11 How long does a glitchless frequency transition take?
12 What is the power-up sequence of the Si5350 or the Si5351?
13 Can the Si5350 or Si5351 duplicate a PWM input?
14 Will changing the Drive Strength through the control registers change the output slew rate?
15 Why is there a separate programming guide (AN1234) for the 16-QFN Si5351?
16 Why does CLK3 on a 16-QFN Si5350/51 show a phase shift from the other outputs?
17 What is the minimum PLL lock range of the Si5350/51?
18 Is therea ppm/degreeC output error or ppm output error over time spec for the Si5350/51 devices?
19 What are the Si5350/51 power-up sequencing requirements for VDD/VDDO? What if I can't meet it?
20 How do you interface Si5350/51 clock outputs to HCSL, LVDS, and LVPECL receivers?