If you are encountering the following error when attempting to use the Si5351-EVB，please try the following explanation to fix the issue.

Error Message in CBPro:

error running post frequency plan calculation tasks (step 1); Plan is not realizable please contact Silicon Labs support for further assitance.

This error is usually seen when you configure outputs in three frequency domains and  two outputs are greater than112.5MHz.

The general criteria below were used to set the frequency plan in CBPro. This is a general model, and individual applications may require some modification.

1. The Si5351 consists of two PLLs—PLLA and PLLB. Each PLL consists of a Feedback Multisynth used to generate an intermediate VCO frequency in the range of 600 to 900 MHz.

Fout=Fvco/(Multisynth x R)

2. Valid Multisynth divider ratios are 4, 6, 8, and any fractional value between 8 + 1/1,048,575 and 900 + 0/1. This means that if any output is greater than 112.5 MHz (900 MHz/8), then this output frequency sets one of the VCO frequencies.

3. For the frequencies where jitter is a concern make the output Multisynth divide ratio an integer. If possible, make both output and feedback Multisynth ratios integers.

4. Once criteria 2 and 3 are satisfied, try to select as many integer output Multisynth ratios as possible.

For example:

OUT1=155.25MHz, OUT2=125MHz and OUT3=94MHz.

CBPro calculates VCO_PLLA=155.25M*4=621MHz and VCO_PLLB=125M*6=750MHz.

But OUT3=94MHz>93.75MHz(750MHz/8), Multisynth divider=750/94=7.9787<8, so the frequency plan cannot be realized.

If OUT3≤93.75MHz, The frequency plan can be realized by Multisynth divider ≥8.

Please see the attached document for Frequently Asked Questions (FAQ) and their answers regarding the Si5372 and Si5371 coherent optical clocks.

The topics from the Table of Contents are listed below.

PCB Design and Layout Guidance    
Where should I look for schematic design assistance?    
Where can I find the IBIS model for the Si5372/71?    
Where can I find the Si5372/71 schematic footprints and symbols?    
Do you have layout recommendations I should follow?    
Do you have a list of recommended crystals?    
I don’t want to use a crystal with the Si5372/71.  Can I use an XO or TCXO as the XA/XB reference instead?  And if so, how do I interface an external oscillator to the device?    2
Are there any power supply filtering requirements or recommendations?    
Is there any specific power supply sequencing requirement?    
What serial interfaces does the device support?    
Are there any power supply filtering requirements or recommendations?    
How do I properly terminate input and output clocks?    

Package Information    
Where can I get detailed material composition information on these devices?    
Is the part RoHS compliant?    
What is the Moisture Sensitivity Level (MSL) rating for the Si5372/71?    
What is the recommend profile for solder reflow process?    

Frequency Plan and Clock Design Decisions    
What is the output frequency range of the Si5372/71?
What development software/tools do you have available to use with the Si5372/71?    
How do I select proper jitter attenuation bandwidth?    
Does the device support automatic input clock selection and does it support hitless switching?  
Is there a recommended full device programming procedure?    
Can I change one output frequency without disturbing other output(s)?    
What is DCO mode and how to use that?    
How much power will my frequency plan draw?    
How can I know the performance of my frequency plan if I can’t measure phase noise or jitter?  
Dose the Si5372/71 support Zero-Delay Mode?    
What is the difference between A grade and J grade?    

SMBus timeout in I2C timing specification table means

If the SCLK keeps low for longer than timeout.min, the interface will start to reset,

If the SCLK  keeps low for longer than timeout.max, the I2C interface will finish the reset.

After the I2C interface reset, customer can restart the talk with our timing products Si534x/7x/8x/9x.

Extent comment:

It is better to not have interrupt if you are talking with slave timing products, if not, please make sure the interrupt last time less than 25ms(Timeout.min).

On power up, the outputs will not function as there is no Si5338 programming. So the blank Si5338 outputs will be tri-stated, and the device will be under Loss of Lock and this prevents outputs being driven from Si5338.

After Si5338 is programmed to a configuration, and there is no interrupt event (LOL, LOS or system calibration), the outputs will be driven by Si5338.

If you are encountering the following error when attempting to use either the Si5338-EVB or the Si5338/Si5356 Field Programmer with ClockBuilder Desktop, please try the attached procedure to fix the issue. 

Error Message:

DoUSBTransaction: SI_FlushBuffers failed when attempting to reset USB communication. Details: USBXpress error: System error in the operating system. See AN169 for more information on how to get the error information.