IO_VDD_SEL bit setting used in the Si534x/8x/9x Customer Evaluation Boards:
The Si539x/8x/4x jitter attenuator timing devices have a power setting IO_VDD_SEL which controls the voltage level to various GPIO pins within the timing chip including the communications pins and status control pins. Please verify with the datasheet for exact pins affected by this power setting.
For systems using a +1.8V host, it is optimal to set IO_VDD_SEL = 0 and all external pullups should be connected to +1.8V. Note that the device GPIO pins are always 3.3V safe regardless of the IO_VDD_SEL setting. The internal GPIO pull-up voltage changes with IO_VDD_SEL (0x0943). It is +1.8V when 0 and +3.3V when 1. In addition to the internal pullup/pulldown, the logic thresholds for the GPIOs are also adjusted by IO_VDD_SEL to give optimum noise immunity at each supply voltage.
The customer evaluation boards (CEVBs) have external pull-ups for these pins set to +3.3V regardless of the IO_VDD_SEL device setting. This is done on the CEVBs because the DUT is always communicating at +3.3V with the MCU for both for SPI/IIC and GPIO inputs and outputs. The DUT should be set to use IO_VDD_SEL = 1, but it will still work when this value is 0. Note that measuring the voltage will always read +3.3V regardless of IO_VDD_SEL. The CEVB MCU has weak software pull ups on the GPIO inputs. Measuring without the CEVB hardware pullups, but with MCU still connected, reads +2.0V when IO_VDD_SEL = 0. Disconnecting the MCU jumper resistor as well as the external pullups gives the correct device value of +1.8V when IO_VDD_SEL = 0. This
Please refer to the datasheet to ensure which pins are affected by the IO_VDD_SEL setting and follow all the datasheet and reference manual recommendations.