Si53154 PCIe Clock Buffer

Clock Outputs

The Si53154 is a PCI-Express Gen 1/2/3 1 : 4 fanout buffer that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing 1 reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings.

Similar Devices: SI53152 SI53154

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Specifications Summary

Inputs: 1

Outputs: 4

Frequency Min (MHz): 100

Frequency Max (MHz): 210

Additive Jitter (ps): 0.1

Zero Delay Mode: No

Package Type: QFN24

Package Size (mm): 4x4

Title Version Resource Type
Silicon Labs PCIe Clock Jitter Tool README 1.3 Software
PCIe Clock Jitter Tool Installer 1.3 Software
1303213 PCIe 24QFN4x4 and 48QFN6x6 Au to CuPd std Product Change Notifications (PCN)
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PB #1511301: Bulletin PCIe ClockGen Buffer Product Change Notifications (PCN)
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AN636: Si5214x and Si5315x Signal Integrity Tuning to Improve Connectivity 0.1 Application Notes
AN951: Driving Long Traces on PCIe Backplanes for Simple Evaluation 0.5 Application Notes
Si53154 PCI-Express Gen 1, Gen 2, Gen 3, & Gen 4 Quad Fanout Buffer 1.3 Data Sheets
Si53154-EVB User's Guide 0.1 User Guides
SI53154 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x, Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families 0.3 Application Notes
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
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PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
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AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
PB-1507013-Si53019-A01AGM-to-update-Pin15-18-descriptions-rev2 Product Change Notifications (PCN)
EOL #1403114: Global Foundries (GFSG) 35um and Last Time Buy (LTB) Product Change Notifications (PCN)
17051960 Relocation of Singapore Test Centre and Order Fullfillment Centre Product Change Notifications (PCN)
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SI53308 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
SI53312 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
時脈樹設計原則 1.0 White Papers
时钟树设计原则 1.0 White Papers
Clock Tree Design Considerations White Papers
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