I am using the SI3402 chip to use POE.
But it does not work properly.
The circuit I have constructed is as follows.
POE: SI3402 (non-isolated)
Ethernet Transceiver: H2019NL
When POE cable is plugged in, it charges for the first time but it becomes impossible to charge soon. I think that the POE side circuit is a problem because I operate normally when only 5V is applied to the charge IC.
Since it is confirmed that 5V is output from the output terminal, it is not a voltage problem.
I attach the schematic that I composed with PDF.
Please make sure that there is something strange in my circuit.
I am using a SiLabs 864x digital isolator ( with no enable pins and no pre-determined output levels). Both sides are powered with 3.3V/GND, but the supplies are separate. When the 3.3V supply is off, my digital inputs can still be active. Since the supply is off on both sides, as expected, my input signals do not propagate. However, I am measuring voltage at the supply pin on the input side. This appears to be back-fed from the input signals.
Given that some input signals are at logic high before powering up the input and output supply voltages to 3.3V, intermittently I have seen failures in propagating the inputs to the outputs. That is, after powering both sides to 3.3V, an input may be at a logic high, but the corresponding output pin is stuck at a logic low.
These devices have a lockout feature for supply voltages below a given threshold, but it appears that the lockout continues even though the voltages are above the threshold. The only reliable way to resume normal communication is to force the inputs (disconnect) to a logic zero and then cycle the input side supply voltage (off and back to on). Followed by re-connecting a cable that feeds the inputs.
My questions are: Is it required that all inputs are at a logic zero prior to supplying power to the input side? If this is true, would a tristate condition work as well? Is there a reason why the outputs would not follow the inputs when both supplies are powered?
Now, I meet a question. when Si8273GB is used, its output voltage is 2.47V. why? I want to get 6V. I want to know if the Si8273 get 6V output voltage.
when i used si827x to driving GaN device, the driving waveform shows that source ability does not meet the IOH spec. at 0ns ~ 5ns.
I hope siliconlab can provide the transient ability curve. That will be great if can provide Spice model (only the driving part).
As per truth table in datasheet Si827x(Page No:12),The state of Voa and Vob are mentioned in the condition of VDDA and VDDB powered.
If VDDA and VDDB are unpowered during start up,what would be the state of Voa and Vob?
I am using SI8602AC-B in our design for isolating I2C signals.
SCL is unidirectional and SDA is bidirectional.
Design flow is like ADC-> SI8602AC -> MCU(ATSAME54)
ADC supply voltage is 5V and MCU is 3.3V
1. Does SI8602 can act as a voltage level translator that convert 5V I2C to 3.3V I2C?
2. Can BVDD and AVDD be different?
Attached snippet of my SCH.
Please respond... Thanks
Is it possible for these isolators to be operated with different supply voltages? For example: VDD1=5.0V, VDD2=3.3V.
And, if you have something I must pay attention or drawbacks when i use them in such way, please let me know it.
we are planning to use Si8233BD-D-IS driver for one of our motor inverter project. in the datasheet , it is specified as High electromagnetic immunity in the key features.
I want to know, this driver will protect against the overshoots( that may cause EMI) during switching transitions.
Also please provide the maximum active current values for both input and output side power supplies. typical values only provided in data sheet.
This is with reference to the Si824x reference kit.
1. In order to modify the gain, would it be correct to change R29 and R30 (4.99kohms), such that doubling the value will double the gain?
2. For bridge application, what would be a the recommended: use two mono channels with 180deg phase shifted signals or use the unused pin 8 of the comparator to drive another half bridge using a 2nd Si824x, in which case the feedback of the 2nd half bridge will drive the non-inverting pin of the error amplifier (IC17B/ 18B) as shown in the attachment?
We are presently using a Si8931 isolated amplifier for high-speed measurements in a high-power motor drive.
One issue we are facing with our system is the possibility of the input amplifier to be supplied with a negative voltage lower than the min -0.5V stated in the data sheet.
The input source voltage can be as low as -4V for 1% of the time and -1.5V for up to 80% of the time.
Can we protect the amplifier with an external series resistor and how can we evaluate its value?
I am totally new to this forum looking for a help. Any tips and advice regarding my issue would be appreciated. I am jacksonlevi, working in a Corporate animation Company. I wanted to know that could the VDDA and GNDA actually be configured such that if, for example, a +15V/-5V bi-polar type biasing be fed into the chip and the source/emitter return of the device connected to separate neutral point?Or a different way could be that a 20V supply be placed between those pins, then using a secondary zener diode with resistors and capacitors create a +15V/-5V gate biasing ckt w/ a derived, floating source/emitter return point.Is there anything in the chip itself that would prevent negative biasing or reverse current flow? I have serached for this issue but did not find any right solution. Please help me
Any help would be greatly appreciated!!