I am using the SI3402 chip to use POE.
But it does not work properly.
The circuit I have constructed is as follows.
POE: SI3402 (non-isolated)
Ethernet Transceiver: H2019NL
When POE cable is plugged in, it charges for the first time but it becomes impossible to charge soon. I think that the POE side circuit is a problem because I operate normally when only 5V is applied to the charge IC.
Since it is confirmed that 5V is output from the output terminal, it is not a voltage problem.
I attach the schematic that I composed with PDF.
Please make sure that there is something strange in my circuit.
I've designed a Class-D amplifier for 1200V with the SI8244. The circuit is mainly based on the recommendations in the datasheet, consisting of two NMOS (C2M0160120D) and a bootstrap circuit. Actually the circuit works properly, but unfortunately the quiescent current is very high! At 1200V, 160kHz, 50% duty, 12V VGS and idle state the current consumption (high voltage supply) is at 20-30mA. It is also increasing for higher switching frequencies. Do you have any suggestions where it comes from and how to reduce it?
- Deadtime is sufficient
- MOSFET driving signals seem to be good with deadtime and low rise/fall time on an oscilloscope
- Bootstrap cap has no influence on the current
- Bootstrap diode seems to have an influence, but the fastest I could find for this voltage range has 50ns reverse time and is installed
We are using the SI3404 chip to use POE, When we used the standard PoE injectors, it works perfectly.
But when we used the non-standard PoE injectors, the chip would burn out occasionally.
Our design is a reference of Si3404-Buck EVB board. Is the SI3404 not support the non-standard PoE injectors ?
Thank you for your Help.
I am working on the AN486 High-Side Bootstrap Design Using ISODrivers in Power Delivery Systems, but I still don't understand the part concerning Bootstrap Circuit—CB Sourcing. The problem is that when Q2 is off and Q1 is on, the potential at the Mosfet source is equal to the potential of the high voltage drain and the potential at the Mosfet gate is equal to Vdd-0.7 which inferior to the drain voltage. So how can we drive the Mosfet if the potential at the Mosfet source is higher than the potential at the gate, normally Vg-vs >0 not the opposite.
I have bought a couple of the evaluation boards for this chip and soldered in a few IR8010 mosfets and some jumpers just for testing.
I added a few 47uF caps on supply inputs 5, 15 and 15V and powered it up from a lab psu.
I also added the 100k trimmer for deadtime adjustment.
Now it seems it does not do anything. If I input 500kHz 5Vpp square wave the output if 1us + 1us regardless of trimmer position.
Seems like voltage on trimmer jumps from 0V to 5V pretty instantly when I start turning it.
It must be something obvious I have missed, what could it be?
Thanks a lot in advance!
I am totally new to this forum looking for a help. Any tips and advice regarding my issue would be appreciated. I am jacksonlevi, working in a Corporate animation Company. I wanted to know that could the VDDA and GNDA actually be configured such that if, for example, a +15V/-5V bi-polar type biasing be fed into the chip and the source/emitter return of the device connected to separate neutral point?Or a different way could be that a 20V supply be placed between those pins, then using a secondary zener diode with resistors and capacitors create a +15V/-5V gate biasing ckt w/ a derived, floating source/emitter return point.Is there anything in the chip itself that would prevent negative biasing or reverse current flow? I have serached for this issue but did not find any right solution. Please help me
Any help would be greatly appreciated!!
I have a gate driver component, with a different suffix but I dont find anywhere what is the actual difference, and what does the suffix mean.
My components are the following:
I have been trying to find components that would enable to transfer energy from two supercapacitors. From upper to lower and from lower to upper, bidirecional. As shown in the picture below.
Ideally a half bridge driver with incorporated Mosfets would be ideally. Maybe I didn't see but it seems Silicon Labs makes gate drivers without incorporated Mosfets.
I intend to use a PIC microcontroller to generate the PWM signal.
The half bridge and Mosfets will be supplied by the superapacitors. With 4 supercapacitors in series and with a linear voltage regulator a constant 5V can be achieved. This will be used to supply the half bridge and the mosfets supplies.
The approach seems to be with the Si827x or the Si8239x family.
Any inside help would be appreciated. #Which half drive, compatible mosfets, evaluation kit.
any app engineer can tell us what is the nature of the output devices in the Si827x drivers? Specifically, judging from their symbols, one would conclude that there is no possibility of reverse conduction in these devises- neither through a body diode nor through a parasitic path. One important consequence of this will be that we can have a negative voltage at node B of the output without problem. True?