Hi, 

I am working on the AN486 High-Side Bootstrap Design Using ISODrivers in Power Delivery Systems, but I still don't understand the part concerning Bootstrap Circuit—CB Sourcing.  The problem is that when Q2 is off and Q1 is on, the potential at the Mosfet source is equal to the potential of the high voltage drain and the potential at the Mosfet gate is equal to Vdd-0.7 which inferior to the drain voltage. So how can we drive the Mosfet if the potential at the Mosfet source is higher than the potential at the gate, normally Vg-vs >0 not the opposite. 

Thank you 

Does anyone have experience with using the Si828x gate driver in high-voltage 3-phase inverters?

Thanks

Hi,

I have bought a couple of the evaluation boards for this chip and soldered in a few IR8010 mosfets and some jumpers just for testing.

I added a few 47uF caps on supply inputs 5, 15 and 15V and powered it up from a lab psu.

I also added the 100k trimmer for deadtime adjustment.

Now it seems it does not do anything. If I input 500kHz 5Vpp square wave the output if 1us + 1us regardless of trimmer position.

Seems like voltage on trimmer jumps from 0V to 5V pretty instantly when I start turning it.

It must be something obvious I have missed, what could it be?

Thanks a lot in advance!

//Jonas

Hi,

We are using the SI3404 chip to use POE, When we used the standard PoE injectors, it works perfectly. 

But when we used the non-standard PoE injectors,  the chip would burn out  occasionally.

Our design is a reference of Si3404-Buck EVB board.  Is the SI3404 not support the non-standard PoE injectors ?

Thank you for your Help.

Hello everyone,

I am totally new to this forum looking for a help. Any tips and advice regarding my issue would be appreciated. I am jacksonlevi, working in a Corporate animation Company. I wanted to know that could the VDDA and GNDA actually be configured such that if, for example, a +15V/-5V bi-polar type biasing be fed into the chip and the source/emitter return of the device connected to separate neutral point?Or a different way could be that a 20V supply be placed between those pins, then using a secondary zener diode with resistors and capacitors create a +15V/-5V gate biasing ckt w/ a derived, floating source/emitter return point.Is there anything in the chip itself that would prevent negative biasing or reverse current flow? I have serached for this issue but did not find any right solution. Please help me

Any help would be greatly appreciated!!

Thank you.

Hi,

I have a gate driver component, with a different suffix but I dont find anywhere what is the actual difference, and what does the suffix mean.

My components are the following:

SI8423AD-B-IS

SI8423AD-D-IS

   I have been trying to find components that would enable to transfer energy from two supercapacitors. From upper to lower and from lower to upper, bidirecional. As shown in the picture below. 

                                                                                   =

                                                                                   =

   Ideally a half bridge driver with incorporated Mosfets would be ideally. Maybe I didn't see but it seems Silicon Labs makes gate drivers without incorporated Mosfets. 

   I intend to use a PIC microcontroller to generate the PWM signal.

   The half bridge and Mosfets will be supplied by the superapacitors. With 4 supercapacitors in series and with a linear voltage regulator a constant 5V can be achieved.  This will be used to supply the half bridge and the mosfets supplies.

  The approach seems to be with the Si827x or the Si8239x family.

  Any inside help would be appreciated. #Which half drive, compatible mosfets, evaluation kit.

Thank you,

Rodolfo Reis

any app engineer can tell us what is the nature of the output devices in the Si827x drivers? Specifically, judging from their symbols, one would conclude that there is no possibility of reverse conduction in these devises- neither through a body diode nor through a parasitic path. One important consequence of this will be that we can have a negative voltage at node B of the output without problem. True?

rg.

This is the application engineer from Nexperia，Where can i get the spice or IBIS model from Si labs？

I would like to create a system simulation model with SI8230BB-DIS1 and SI8273BBD-IS1, thanks in advance

Hi,I am using the SI8621BC-B-IS , and the current drawn by VDD2 is 2.34mA , is it possible to lower this value . I want this side of the isolator to draw the least current possible .

Also I am powering the IC from a fixed voltage reference ic which has a value of 4.096 VDC , and at this supply voltage the Isolator is drawing 2.34mA from VDD2 Pin , if the ambient temperature increases or decreases within the specified range of -40C to +125C does this cause the IC to draw more current ???  

If the supply voltage to the DCDC converter is 12V converting to in and isolated to 3.3V

how to configure to drive input of isolators at 3.3 V

Dear Sirs,

I want to use Si8660 and Si8662 to isolate my microcontroller from output signals
that goes to wires. It could happen that when wires cutted then I will have 24V on wires
that goes directly to microcontroller and they are rated for 3.3V.

Simply I want to make my PCB to be 24V immune on wires that are for 3.3V.

Can I use Si8660 and Si8662 for that?  

I wont have isolated voltage for VDD1 and VDD2. I want to use the same voltage source
but connect fuse between VDD1 and VDD2 and second fuse between GND1 and GND2.

If VDD1 connected to 3.3V and by fuse to VDD2, then when it happen on VDD2 side that wire
gets connected to 24V. Is that going to destroy that Isolation IC, or after wires fixed everything will
work like before connecting to 24V?

Best regards,

Chris

Can you post an IBIS model for the output stage of the Si8274 isolator?