I recently bought your amazing dual gate driver Si8275ABD. I've to use it in my bachelor degree's final project. I'm unable to find any model of the device for simulation purposes. It is requested that any available model kindly be provided to us at your earliest ease for this educational learning opportunity.
Hi Silcon labs team,
I am currently working on a high end class D powerstage in which I'm considering a gatedriver in the SI824x range. The advertised feature of these chips above the regular SI823x series is the precision deadtime, but there is no tolerance specified in the datasheet of SI824x.
From the datasheet of SI823x, the programmed dead time for a RDT of 6kOhms is specified to be 70ns nominal, with a min of 55ns and a max of 75ns, for a tolerance of +/-21%. What would be the improvement in dead time tolerance be in this range if we went for the SI824x series?
Also, we are considering using variable deadtime. is this supported by these drivers and if so, can we control the deadtime cycle by cycle?
Thanks in advance.
i have 3 h-bridges here with the same issue. When i feed a 50% duty pwm to the driver and there is a current of approx 10A flowing through the FETs i have sporadic errors in the low side gate drive.
The high side goes as expected to 0V (VGS) and then the low side gate starts to rise, at approx 90% of the rise the VGS drops to 0 with a sharp edge no discharge of the gate capacitance in there. Then the turn on of the low side starts again und reaches its turn on level.
At first i thought i would be an disturbance on the EN Pin due to the fact that in the fail event both gates are low but fixig EN to 3V3 volts changed anything.
Does anyone have a hint where to look at? PWM is 24kHz at 30V input. The Gates are supplied by -5/10V. The input PWM is fine and 3V3s is also fine.
Thanks in advance.
After over 10 designs with the SI3402B, I need to make a POE circuit that is only rated to 3W instead of the 15W normal solution as your reference design.
So Im looking to reduce some of the components like the D3 PDS1040 and the transformer FA2924 from your reference schematic
For the Diode this is straight forward but the for transformer I not sure how flexible the circuit is.
I been looking at the Coilcraft POE30P-33L_ seriel but this also have a bias coil thas is not needed and also the turn ration is different compared to the original version.
Since we are using rough 50K pr year I can perhaps get a costom version that will fit my need.
Any idea of some lower rated transformer you can suggest ?
We are using SI8274 driver for an Half bridge LLC Application. we are using a 5 V power supply for Vdd1. And two separate isolated 15V power supply for Vdda and Vddb.
The PWM pulse was given from a micro-controller. At the first instance, we got the both the outputs with dead band. Very shortly one output was become zero. Then we found that the power supply for Vddb was over heated, which happened because the Vddb and gndb was showing short..
Then we replaced the driver with a new one. This time the same happened with Vdda and once again the driver failed. I have also attached the schematic.
Kindly help us to identify/resolve the issue.
I am using IC SI8631AB-B-IS1 for isolation , this pin has EN1 and EN2 , Can this pin be left floating for proper operation on this isolator, since thies both EN1 and En2 internally pulled up.
I need the following specifications please for the Si8751 (I can't find these in the data sheet):
1) Worst case (min) over temperature current sinking capability (max output resistance) for the output driving the MOSFET gate low
2) Worst case (min) over temperature input resistance of the input pin
3) The output resistance for current sinking is not dependent on the TT pin - right?
My application is 2MHz, 21kW, full bridge inverter, VDD<200V, SIC MOSFET C3M0065090D . SI8274 is used as an isolator, not drive SIC Mosfet directly. Input 5V 2MHz signal, then Si8274, each output of SI8274 is connected to each driver buffer IXDD614 before driving SIC MOSFET. All used isolated supply for gate drivers, +20V and +5V (attached picture): +20V to VDDA or VDDB; +5V to S of SIC mosfet
VDDI of SI8274 is 5V.
The problem is low side output of SI8274 frequently burned even it can be burned when there is no VDD suppy to MOSFET. Here are some cases I listed which burning occurs (only low side output of SI8274 is fired)
1. Isolated supplies 20V to VDDA, VDDB; 5V to S of SIC MOSFET; 5V to VDDI and EN pin (all supplied same time) no input signal
--> Sometimes, low side output VDDB, VOB, GNDB is burned even without 2MHz input
2. Isolated supplies 20V to VDDA, VDDB, 5V to S of SIC MOSFET --> then 5V to VDDI --> then input signal 2MHz --> 5V to EN pin
--> SI8274 burned ( low side output VDDB, VOB, GNDB)
3. Several cases by changing power supplies sequence or when output power is ~500W --> sometimes SI8274 is burned. I've tried to analyze it but didnt find out reason yet
Any advise for this issue
I am totally new to this forum looking for a help. Any tips and advice regarding my issue would be appreciated. I am jacksonlevi, working in a Corporate animation Company. I wanted to know that could the VDDA and GNDA actually be configured such that if, for example, a +15V/-5V bi-polar type biasing be fed into the chip and the source/emitter return of the device connected to separate neutral point?Or a different way could be that a 20V supply be placed between those pins, then using a secondary zener diode with resistors and capacitors create a +15V/-5V gate biasing ckt w/ a derived, floating source/emitter return point.Is there anything in the chip itself that would prevent negative biasing or reverse current flow? I have serached for this issue but did not find any right solution. Please help me
Any help would be greatly appreciated!!
There is no mention in the datasheet of these parameters. The only reference I can find is the 500kHz test for the PWM input to the EVAL board. I need to run the PWM input over 2MHz and the duty cycle needs to run as close to 0 and 100% as possible.
One could guess that the minimum pulse width corresponds to the prop delay plus a rise time (e.g., 30ns + 10.5ns = 40.5ns). To hit 5% duty factor, the PWM period would have to be at least 20 x 40.5ns = 810ns or a PWM frequency of 1.2MHz. If the minimum pulse period equals two prop delays plus a rise time and a fall time (e.g., 2x30ns + 10.5ns + 13.3ns = 83.8ns), then the typical maximum PWM frequency could be as high as 11.9MHz.
May I, please, have the achievable values for these parameters?
I bought from Mouser some Si8261ACC drivers, and I'm testing the first.
I feeded with 12.3 V, wich is 0.3 higher from 12 V UVLO, I feeded the simulated diode (pin 2) on input with 12 V signal from a button switch (same source) and limited current with 1.5 KOhms resistor in Cathode (pin 3), it doesn't do anything in response to change in pin2, then I changed resistor in pin 3 with a 1 K, now with 670 Ohms and the device doesn't do anything, no in the pin 3, neither in pin 6.. The output (pin 6) has a 1K resistor before a Led, which would receive the output at 12 V, but measuring in Cathode (pin 3) and here, there is no any change, so the simulated diode seems don't conduct. I'm afraid that if I put a lower resistance in pin 3 and then it conducts, the device become broken. Am I missing something or these devices doesn't work?
The device is feeded with 12.3 V in pin8 and ground in pin 5 by a PC power source.
I am looking at using the SI88242 device for an analogue sensing system. The IO requirements of both sides of the isolator are 3.3V, however the output side requires enough headroom in its isolated supply to allow for a low-noise LDO to be used - basically to get rid of the ~100mVpp ripple produced by the SI88242.
I would like to run the DC/DC converter at 5V - so feed 5V at the input side, and get 5V at the output side. This will allow me to nicely regulate the voltage down to 3.3V. However, driving all the supply pins of the SI88242 with 5V would require additional level shifting of the I/O signals that I would like to avoid. As such I would like to run the device with the following setup:
I cannot tell from the datasheet whether this would be allowed, as all of the characteristics specify VDDP=VDDA, and it doesn't mention whether VDDB can be fed from an external voltage regulator.
I've attached a schematic of the planned power supply setup.
Could you confirm whether my proposed setup will not cause any issues for the SI88242?
I'm looking to isolate analogue and digital circuits with very low frequency signals - switches in fact. The Si8380 looks like it will potentially do the trick. I've used TI's digital isolators before and simply connected pins directly to other devices. So, for example, from a micro to an input pin of the isolator and an output pin directly to its destination device.
I'm not at all clear - and maybe I'm just being numb - whether I night need a series resistor from a micro to the input of the Si838x. The datasheet seems to be saying it works like an opto coupler, where you obviously need the resistor in series with the input. However, the datasheet shows a bridge rectifier on the the input, so I'm not at all clear what's going on there.
What about the outputs too? When I'm going the other way.from analogue domain to the micro, can I connect an analoguw signal directly to the input and then the output directly to the micro or do I need anything else on input or output.
I've Googled around for example real-world circuits and found the square root of nowt! :D