I am looking at designing these 2 parts into my project with the SI53304 outputting an LVDS clock on a motherboard to an SI5332 IC on a daughter card.
Looking at the SI53304 LVDS output specification, it says that the single ended output swing Vse is minimum 247mV when driving a differential 100 ohm load.

And looking at the SI5332 datasheet, it says the voltage swing should be minimum 0.5V Vpp_diff (AC coupled < 312.5MHz) at its input.

So my concern is, if I AC couple between the SI53304 and the SI5332 and place a 100 ohm load at the receiver, this doesn't look like it will work across all process corners for the 2 ICs since 2 x 247mV < 0.5V.

Have I got something wrong here?

Hello,

I am designing a board with Si5341 clocking many different parts of the system. 

The input to the Si5341 is a crystal oscillator on IN0 and a SyncE/PTP recovered clock on IN1.

One of the outputs of Si5341 is the main clock to an FPGA on the board. The I2C port of the Si5341 is connected to the FPGA.

I have two questions about Si5341 -

1. The FPGA cannot program the Si5341 over I2C without getting an input clock. What is the default configuration of the Si5341 without programming? Which document gives me this information? Ideally, I would like the crystal frequency to be directly fed to the FPGA so that it can start working. Is this possible (without factory programming)?
2. I have two inputs - a crystal and a stable clock on IN0 and IN1 respectively. The frequency of both clocks is the same. Initially, I would like to use the crystal to get the system started and once the recovered, stable clock is available on IN1, I want to be able to switch to this. The input selection happens dynamically. Is this possible?

If both the above items - default startup clock equal to the input and dynamic switching of the inputs - are possible, the Si5341 will be the only clock chip on my board with a single crystal oscillator. Else, more components will be required.

Hello,

We'd like to use the cross point as a switcher beetween many frequency sources (multi FSK).

Is it possible to control the cross point dynamically, and what is the latency for it?

Best regards

Hi ,

I am using SI5338B-B-GM clock synthesizer in my design.am not clease whether IN1 is connected to inverting or non inverting terminal?

Schematic connection is captured in the image attached herewith.Please confirm whether my input stage is ok ? 

 

Generic model number is Si598, which have a startup freq of 156.25MHz.  Product spec mentioned it can be programmed to other frequency with a range of 10-810MHz.  Tried to reprogram the chip to 161.133MHz through I2C based on example in the product spec seems not to take effect.

Question:

1. Can I effectively reprogram this clock chip and make it stick while device is powered-up?

2. Do i need to terminate SCLand SDA pin after I program? if so, to what state (VDD or GND)?

It's not clear to me from the docs whether the SI5332 NVM can be reprogrammed, or it is OTP (or 2-times programmable because of multiple banks).  This doc compares the SI5332  to the Si534x, saying Si5332 has 'flexible NVM space'.  Does that mean it has erasable EEPROM that can be arbitrarily updated with new configurations?   If not, do other SI parts have EEPROM which can be updated?

https://www.silabs.com/documents/public/user-guides/ug286-clockbuilderpro-dongle.pdf

 

I assume the OTP config can be overridden at runtime by writing (volatile) settings over I2C, correct?
 

I use Si5340A-D-GM to generate a 322MHz output with a 48MHz±10ppm XTAL input. I don't have a spectrometer to measure the phase noise.

To see the output Jitter performance, I use a 80G Sa/s oscilloscope with 25GHz analog bandwidth. It turns out that the Jitter TIE RMS is around 2ps.

Can I have any chance to get further Jitter improvement by adjusting SI5340 configuration, such as PLL bandwidth or should I check my hardware design?

Regards.

Hi,

I can successfully write registers and a project file to the clock generator via a command such as:

CBProDeviceWrite --family si538x4x --mode spi4wire --io-voltage 3.3 --project config.slabtimeproj

However, when I power-cycle then the configuration reverts to the original config.

If I use the NVM programmer GUI then it writes to the NVM area and power-cycles retain the correct configuration.

Is there any way I can do this via the command line, rather than running the GUI application?  I need to program hundreds of boards, and I need a way to do it automatically and not manually.

In case it is important, I am using the CBProgrammer dongle.

Many thanks,

Andy

 

Hi,

I'm currently using the SI5330F to buffer a single ended clock.  I have a single-ended signal that needs a similar propagation delay as the clock and rather then looking for a device with a similar delay it would be easiest to use the same buffer. 

I know the SI5330F has a minimum input frequency of 5MHz.  This single ended signal will be below that value.  My question is, can I use the si5330F to buffer this signal, if I don't care about the LOS output?  Is the minimum input frequency required for LOS detection only?  If there is a LOS condition, will the output actually every edge seen on the input, or will there be some edges skipped while it comes out of a LOS state?

Kind Regards,
Stephen Craig

Hello,

I have two questions about the SI5338A-B-GM. 

*I wonder that is it possible that receiving clocks @3.3V LVPECL/LVDS from an SI5338A-B-GM with a core voltage VDD=2.5V?

*If  core voltage VDD=3.3V, then should IN3 input accept an clock @ 3.3V cmos level from oscillator ? Or fed IN3 with an clock @ 2.5V cmos level is also OK?

Could you explain the relation (if there is) between core voltage and output clocks voltage levels and input IN3 clock voltage level? 

Thank you,

 

I have a very specific delay requirement and it appears the typical (2.5ns) and maximum (4ns) are acceptable for my application, but the delay can't be too little...  Are there plots of minimum delay based on input signal standard or something?

Hello,

I am interested in the per-pin maximal pressure allowed for the Si5319.

Thank you.

Hi there,

I am interested in using your Si530 on our reference boards. We need a 1GHz clock 1.8V CML outputs ac-coupling into our receiver. Could you let me know how to terminate the Si530 CML differential outputs on the boards.

Thanks,

Clement

Hi,

The data sheet for the SL18860DC doesn't seem to specify the input to output delay from CLKIN to CLKOUT(1/2/3) or the maximum skew between each of the CLKOUT outputs. Are these parameters characterised and is this information available?

Thanks

Hmm, the Silabs Part Number Search Results seem to have broken.

I notice Digikey have added many Si5351A's to their stock to arrive, but lack any MHz infos.

Yesterday, it gave PDFs for the parts, now it gives a cryptic, less useful 

Existing Custom Parts    | 1 result

Will this be fixed, and is there a smarter way to find the Digikey MHz / Config values ?

A table would be a very good idea ?