Si5348 Revision D Reference Manual, Rev. 1.4, page 43, chapter 6.5 Output Enable/Disable, 3rd sentence:
"The output enable pins can be mapped to any of the outputs (OUTx) through register configuration."
What is the address of this register, what is the description of it? I didn't find it yet.
In Si5351 App note AN619, Rev .7, page 3, the following equation is presented to calculate the PLL feedback MS values:
MSNx_P1[17:0] = 128 x a + Floor (128 b /c) - 512
Can someone please explain how this equation is derived?
I have read in AN619 on p. 60, section "Register 177. PLL Reset", that you can reset PLL A and B. Unfortunally, the behaviour is not documented. My questions:
We got Si5395 Evaluation Board, then try to check it functional or not, so we prepare Signal Generator "R&S SMJ100A" generated 1 MHz Sine wave, check it by Oscilloscope,
Oscilloscope display correct sine wave , frequency measured result shows: 1 MHz. So , connect Signal Generator output to Si5395 Evaluation Board Clock Input "IN0",
configure Clock Builder Pro output "OUT9A", press button "write design to EVB" and "Open EVB GUI" , connect "OUT9A" to Oscilloscope, it shows square wave
on Oscilloscope, stop Signal Generator , but Oscilloscope shows square wave continuous. Does it missing steps or some suggestion for us?
(1). Does Si5395 Evaluation Board support sine wave input, then output sine wave? how about jitter clean capability?
(2). Attach Si5395 Evaluation Board configuration file, would you check it to find out the problems? Thanks.
I guess, I have found some typos in the documentation "AN619" for the SI5351.
I hope, that help!
I want to switch off output OUT6 at runtime on a custom board.
With an I2C sniffer I recorded the I2C sequence ClockBuilder Pro creates for reading and writing register 0xB6, which contains the output enable bit for OUT6, see attachement
I noticed, that CB Pro always creates a write sequence to register 0x01 with data value of 0x40 preceding the read or write operation to register 0xB6.
My local FAE also cannot seem to find what I would have thought is a basic function. I have a custom part number with SiLabs for a 5332 part. I have received my first samples of the parts. I simply want to load those parts in the programming dongle and verify the programming is the same as the project file I supplied to SiLabs. The part does show the correct design ID, but I would like to 100% verify.
Thanks for any insight!
I would like to put two SI5394 chips connected to the same I2C link so I need to set different values for the I2C addresses A0 and A1 pins.
How can I do that ? It is not clear for me looking at the datasheet.
- If left unconnected what are the default values of these pins A0/A1 ? High ?
- If I want to externally force them, how can I do that ? with pull up/down resistors or directly to VCC or GND ?
Thanks for your help.
Part NO: SI5332E-D-GM1
Playing around with CBPro, I see that there is a Frequency Select option (the Multi Synth outputs, not the integer dividers) which can be either controlled through i2C writes or by toggling one on the GPIs. Have many questions regarding its operation and speed.
1. How large a frequency change is possible with this? I need the two profiles to be anywhere within 100 - 200 MHz range, 100 KHz steps would be nice.
2. What is the time taken to switch between the frequencies, once I toggle the GPI? Something below 100 uSecs would be ideal.
3. How slow would updating the profile over i2c be? Can I in effect have a large number of profiles (even if switching between them would be too slow)?
3. Can using this feature possibly worsen the jitter in some way?
4. Is this the same DCO feature mentioned in Si5341/40 datasheets or completely different?
5. If such fast switching isn't possible with this feature, can I in some way combine two outputs but OE disable one of them as required? (OE switch on delay was mentioned as less than 20us in the datasheet).
The two profiles seem to work fine for large frequency changes (85.74 MHz - 165.34 MHz and so) but fails freq planning when I try something like this: 85.7432 MHz and 165.3456 MHz. The error it gives is: "Cannot store Frequency Select solution within the range of N0". So I am guessing it has something to do with the numer/denom limits? I don't really need such offsets but would like to know the limitations of this.
Edit: This does answer some details and mentions the feature as DCO but with a different process. But doesn't clarify the "settling" time (is it instantaneous once the dividers banks are switched over?). https://www.silabs.com/community/timing/knowledge-base.entry.html/2019/10/29/si5332_dco_processintroduction-Swzo.
I would like to connect the SI5394 to an I2C link. In that case the I2C_SEL pin should be tied to 1.
- If this pin left unconnected, is I2C_SEL level = 1 ? (internally pull - up 20K)
- or should I connect it directly to VDD or wiht external pull up resistor ?
Thanks for your help.
This is related to support ticket 00218574.
I'll also post here on the forum publicly for others too see:
I've noticed, and am slightly confused in the register values shown in the manual when compared to what clockbuilder shows. Which one is the canonical source?
I have a SI5340-D-EB and I wish to manipulate R0_REG: In ClockBuilder (Version 2.40) it says R0_REG is 0x0250[23:0].
However in the Si5341-40-D-RM reference manual from: https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf, It says R0_REG starts at 0x024A and ends at 0x024C (page 74, table 15.64). So which one is correct? And are there any more incongruencies?
we have a product with Si5338 PLL. Everything works fine so far.
Right now inter board phase synchronization is required.
1. global 15MHz clock source for all boards
2. global digital SYNC signal for all boards
3. all Si5338 have same output frequency, for example 8MHz
Is it possible to synchronize phase of 8MHz clock on different boards using SYNC with Si5338? Lets say we would like to align posedge of 8MHz to posedge of SYNC.
Does silicon labs have other product, capable of such synchronization?
It is said "The input-to-output skew is not controlled. External circuitry is required to control the input-to-output skew".
In my application, it is strictly required that the input-to-output skew shall be less than 0.1ns. How to add external circuitry to control it?
I downloaded the new version 4.1 PCIe Clock Jitter Tool released yesterday and this tool is not able to load the .trc waveform file. However, the previous version 4.0 works without any problems with the same file. Please check.
I have an existing PCB with Si5324.
The Si5324 has a 114.285MHz xtal connected to its XA and XB pin.
Can the Si5324 be configured as a clock generator?
Can it be configured to generate a 148.5 MHz clock?
I've read about it in the following address: https://www.silabs.com/community/timing/forum.topic.html/can_si5324_be_useda-jSSl
I've tried using the "Si5324_156M250_FreeRun.txt" file, but it did not help.