This Community thread is for feedback on the new Silicon Labs PCIe Clock Jitter Tool. The tool was recently announced and is available as a free download here:
I am configuring Si5345 with FPGA through I2C. After writing slave address, it should response an "ACK"(low). But it always give high("NACK"). The output clock always keep 500MHz, not my configured value. What can i do to that?
Need information about thermal characteristics of SI5214x:
Junction temperature (Tj) and thermal resistance of junction to case (ØJC) are mentioned in datasheet, which are absolute ratings. I need recommended ratings. please any one help me for thermal analysis.
I want to remove jitter from 158.4945MHz clock (=158.4945MHz input and 158.4945MHz output).
I have 38.4MHz fundamental mode crystal on XA/XB (CMODE pin is low).
I inputting on CKIN2 (CLK_SEL pin is wired High) and the Si5327 says LOL_2 = 0 no problem.
BUT I do not see any output clocks (I want output on CLKOUT1) and the SI5327 does not lock (LOL = 1).
I am programming using I2C (from an FPGA) with register values from the SiLabs DSPLL (v5.1) software.
The software is a little confusing: In the first window, there seems no option to select one input on CKIN2. (CKIN1 is only option - see image - although later the software lets me choose CKIN2).
At first, I guessed this was the problem because it means DSPLL software writes register 11 = 0x42 in the txt file (= power-down CKIN2 input buffer).
BUT even if I change register 11 to 0x40 (=buffer enabled), still I do not get any output from Si5327 and LOL = 1.
(I also experimented with some other settings also such as BWSEL - but it did not fix)
Can anyone offer any help ?
Thankyou
Register file (in this example Register 11 was edited to enable CLK2 input buffer)
I want to remove jitter from 158.4945MHz clock (=158.4945MHz input and 158.4945MHz output).
I have 38.4MHz fundamental mode crystal on XA/XB (CMODE pin is low).
I inputting on CKIN2 (CLK_SEL pin is wired High) and the Si5327 says LOL_2 = 0 no problem.
BUT I do not see any output clocks (I want output on CLKOUT1) and the SI5327 does not lock (LOL = 1).
I am programming using I2C (from an FPGA) with register values from the SiLabs DSPLL (v5.1) software.
The software is a little confusing: In the first window, there seems no option to select one input on CKIN2. (CKIN1 is only option - see image - although later the software lets me choose CKIN2).
At first, I guessed this was the problem because it means DSPLL software writes register 11 = 0x42 in the txt file (= power-down CKIN2 input buffer).
BUT even if I change register 11 to 0x40 (=buffer enabled), still I do not get any output from Si5327 and LOL = 1.
(I also experimented with some other settings also such as BWSEL - but it did not fix)
Can anyone offer any help ?
Thankyou
Register file (in this example Register 11 was edited to enable CLK2 input buffer)
I programmed the si5338 with values from the clockbuilder desktop 6.5. The values were entered via I2C bus from our own micro, not any of your devices. The output frequencies are not what I expected. All seem to be about 30% hi. I am using a 33.33333mhz cmos clock input on IN3. I programmed it to get 100mhz out on channels a and b but get something closer to 130mhz. What could be causing this? All inputs to the chip seem proper. I noticed that clockbuilder seems to account for only 145 of the over 300 regs in the chip. Is not programming the remainder of the regs an issue? Attached is the clockbuilder output.
I'm getting "Error Processing Wave Data" when trying to analyze the attached csv phase noise data. It comes from an E5052B SSA. I can't tell what's wrong with the formatting.
I have an issue with the SI5351B that I can't manage to resolve.
I actually use a 27MHz 8pF xtal to generate a 72MHz clock on out4 and 12.288 on out 6. I use the CBPro tools to generate all the register.
When I set all the register with the procedure described in the datasheet, I do have some clock on the pin but at wrong frequencies : ~96MHz and ~16MHz.
There is a factor 1.3 that come from no where and the frequency does not seems to be very stable.
When I check the status register, it says the plla is unlocked.
/* Write new configuration to device using
the contents of the register map
generated by ClockBuilder Desktop. This
step also powers up the output drivers
(Registers 15-92 and 149-170 and 183 */
for (i = 0; i < SI5351B_REVB_REG_CONFIG_NUM_REGS; i++) {
SI5351B_set_reg(si5351b_revb_registers[i].address, si5351b_revb_registers[i].value);
}
I used the field programming kit to write directly to the NVM of twenty SI5338. Then I found the configuration file is wrong. I decide to write to registers in RAM through the I2C interface. Here is the question. Seven in the twenty can not be programed successfully. The phenomenon is that there is no clock output.
I believe that I managed to write something wrong to the registers of the chip and have problems to program it with CBPro(2.8.81). I can still program it with an external mcu.
When I start CBPro, I see that evaluation board is detected but Rev Unknown. I open the Default Plan and the EVB GUI. Then I get a message:
DUT/Board mismatch: There is a mismatch between the device present and on the EVB and the type of board. The device is unknown, but a Si5340 board is present (board id is 40d). Please contact Silicon Labs for assistance.
I am evaluation the Si5340 which we intend to use for audio as well as driving a dsp clock. I have noticed that when I make a frequency change to, for example OUT2, then I notice that the clock ouput on OUT0 is affected at the instance of frequency change. I am worried that such a glitch will stop the DSP or other processors that are receiving their clocks from the other Si5340 outputs. Am I doing something wrong when I do any frequency updates or is this expected behavior?
I control Si5340 using i2c and the header files that are generated from CBPro (2.28.1).
Forum
PCIe Clock Jitter Tool
Hi everyone,
This Community thread is for feedback on the new Silicon Labs PCIe Clock Jitter Tool. The tool was recently announced and is available as a free download here:
http://www.silabs.com/products/timing/pci-express-learning-center
We are very excited for people to try it out! Please let us know any feedback or suggestions that should be addressed in future updates.
Thanks!
Silicon Labs Timing Support Engineers
Si5345 I2C configuration with FPGA.
Hi everyone,
I am configuring Si5345 with FPGA through I2C. After writing slave address, it should response an "ACK"(low). But it always give high("NACK"). The output clock always keep 500MHz, not my configured value. What can i do to that?
Need information about thermal characteristics of SI5214x:
Need information about thermal characteristics of SI5214x:
Junction temperature (Tj) and thermal resistance of junction to case (ØJC) are mentioned in datasheet, which are absolute ratings. I need recommended ratings. please any one help me for thermal analysis.
SI5351-C PLL CONFIGURATION
Dear sir/madam,
I am using Si5351C IC. It is required to configure the output of PLL to 125MHz. Register address are taken from Clock builder Pro software.
PLL is I2C programmed and Clkin 50MHz is used as the reference clock. But I am arriving at output of 25MHz only.Please help me in resolving the issue.
Regards
Jayashree
SI5328C-C-GM Derating factor
Hi all,
Can anybody please provide derating information for the IC SI5328C-C-GM.
Regards,
Vyshnav Krishnan
Si5328 MTBF or FIT
Hi all,
Can anybody please help me by providing MTBF or FIT rate for SI5328C-C-GM IC.
Regards,
Vyshnav Krishnan
Si5327 lock problem and DSPLL software question
Hi,
I am having problems with Si5327.
I want to remove jitter from 158.4945MHz clock (=158.4945MHz input and 158.4945MHz output).
I have 38.4MHz fundamental mode crystal on XA/XB (CMODE pin is low).
I inputting on CKIN2 (CLK_SEL pin is wired High) and the Si5327 says LOL_2 = 0 no problem.
BUT I do not see any output clocks (I want output on CLKOUT1) and the SI5327 does not lock (LOL = 1).
I am programming using I2C (from an FPGA) with register values from the SiLabs DSPLL (v5.1) software.
The software is a little confusing: In the first window, there seems no option to select one input on CKIN2. (CKIN1 is only option - see image - although later the software lets me choose CKIN2).
At first, I guessed this was the problem because it means DSPLL software writes register 11 = 0x42 in the txt file (= power-down CKIN2 input buffer).
BUT even if I change register 11 to 0x40 (=buffer enabled), still I do not get any output from Si5327 and LOL = 1.
(I also experimented with some other settings also such as BWSEL - but it did not fix)
Can anyone offer any help ?
Thankyou
Register file (in this example Register 11 was edited to enable CLK2 input buffer)
#END_OUTPUT
#CONTROL_FIELD
# Register-based Controls
# FREE_RUN_EN: 0x0
# CKOUT_ALWAYS_ON: 0x0
# BYPASS_REG: 0x0
# DHOLD: 0x0
# SQ_ICAL: 0x1
# BWSEL_REG: 0xA
# HIST_DEL: 0x12
# ICMOS: 0x3
# SFOUT2_REG: 0x7
# SFOUT1_REG: 0x7
# HLOG_2: 0x0
# HLOG_1: 0x0
# HIST_AVG: 0x18
# DSBL2_REG: 0x0
# DSBL1_REG: 0x0
# PD_CK2: 0x1
# PD_CK1: 0x0
# VALTIME: 0x1
# LOCKT: 0x1
# CK2_BAD_PIN: 0x1
# CK1_BAD_PIN: 0x1
# LOL_PIN: 0x1
# INT_PIN: 0x0
# CK_BAD_POL: 0x1
# LOL_POL: 0x1
# INT_POL: 0x1
# LOS2_MSK: 0x1
# LOS1_MSK: 0x1
# LOSX_MSK: 0x1
# LOL_MSK: 0x1
# N1_HS: 0x0
# NC1_LS: 0x7
# NC2_LS: 0x7
# N2_LS: 0x27F
# N2_HS: 0x0
# N31: 0x4F
# N32: 0x4F
# LOS1_EN: 0x3
# LOS2_EN: 0x3
# FASTLOCK: 0x1
#END_CONTROL_FIELD
#REGISTER_MAP
0, 14h
2, A2h
3, 15h
4, 92h
5, EDh
6, 3Fh
8, 00h
9, C0h
10, 00h
11, 40h
19, 29h
20, 3Eh
22, DFh
23, 1Fh
24, 3Fh
25, 00h
31, 00h
32, 00h
33, 07h
34, 00h
35, 00h
36, 07h
40, 00h
41, 02h
42, 7Fh
43, 00h
44, 00h
45, 4Fh
46, 00h
47, 00h
48, 4Fh
128, 00h
129, 1Eh
130, 01h
131, 1Fh
132, 02h
137, 01h
138, 0Fh
139, FFh
136, 40h
#END_REGISTER_MAP
#END_PROFILE
Si5327 lock problem and DSPLL software question
Hi,
I am having problems with Si5327.
I want to remove jitter from 158.4945MHz clock (=158.4945MHz input and 158.4945MHz output).
I have 38.4MHz fundamental mode crystal on XA/XB (CMODE pin is low).
I inputting on CKIN2 (CLK_SEL pin is wired High) and the Si5327 says LOL_2 = 0 no problem.
BUT I do not see any output clocks (I want output on CLKOUT1) and the SI5327 does not lock (LOL = 1).
I am programming using I2C (from an FPGA) with register values from the SiLabs DSPLL (v5.1) software.
The software is a little confusing: In the first window, there seems no option to select one input on CKIN2. (CKIN1 is only option - see image - although later the software lets me choose CKIN2).
At first, I guessed this was the problem because it means DSPLL software writes register 11 = 0x42 in the txt file (= power-down CKIN2 input buffer).
BUT even if I change register 11 to 0x40 (=buffer enabled), still I do not get any output from Si5327 and LOL = 1.
(I also experimented with some other settings also such as BWSEL - but it did not fix)
Can anyone offer any help ?
Thankyou
Register file (in this example Register 11 was edited to enable CLK2 input buffer)
#END_OUTPUT
#CONTROL_FIELD
# Register-based Controls
# FREE_RUN_EN: 0x0
# CKOUT_ALWAYS_ON: 0x0
# BYPASS_REG: 0x0
# DHOLD: 0x0
# SQ_ICAL: 0x1
# BWSEL_REG: 0xA
# HIST_DEL: 0x12
# ICMOS: 0x3
# SFOUT2_REG: 0x7
# SFOUT1_REG: 0x7
# HLOG_2: 0x0
# HLOG_1: 0x0
# HIST_AVG: 0x18
# DSBL2_REG: 0x0
# DSBL1_REG: 0x0
# PD_CK2: 0x1
# PD_CK1: 0x0
# VALTIME: 0x1
# LOCKT: 0x1
# CK2_BAD_PIN: 0x1
# CK1_BAD_PIN: 0x1
# LOL_PIN: 0x1
# INT_PIN: 0x0
# CK_BAD_POL: 0x1
# LOL_POL: 0x1
# INT_POL: 0x1
# LOS2_MSK: 0x1
# LOS1_MSK: 0x1
# LOSX_MSK: 0x1
# LOL_MSK: 0x1
# N1_HS: 0x0
# NC1_LS: 0x7
# NC2_LS: 0x7
# N2_LS: 0x27F
# N2_HS: 0x0
# N31: 0x4F
# N32: 0x4F
# LOS1_EN: 0x3
# LOS2_EN: 0x3
# FASTLOCK: 0x1
#END_CONTROL_FIELD
#REGISTER_MAP
0, 14h
2, A2h
3, 15h
4, 92h
5, EDh
6, 3Fh
8, 00h
9, C0h
10, 00h
11, 40h
19, 29h
20, 3Eh
22, DFh
23, 1Fh
24, 3Fh
25, 00h
31, 00h
32, 00h
33, 07h
34, 00h
35, 00h
36, 07h
40, 00h
41, 02h
42, 7Fh
43, 00h
44, 00h
45, 4Fh
46, 00h
47, 00h
48, 4Fh
128, 00h
129, 1Eh
130, 01h
131, 1Fh
132, 02h
137, 01h
138, 0Fh
139, FFh
136, 40h
#END_REGISTER_MAP
#END_PROFILE
si5338 does not output expected freqs
ClockBuilder regression (v2.37)
Hmm.. Seems Silabs have broken part of ClockBuilder.
Using Si5351A, it is legal to have any 25~27MHz Xtal, and I have a saved design that has 26.000 MHz thus :
Input0: Source = Crystal Source Frequency = 26 MHz Fpfd = 26 MHz Load Capacitance = Load_08pFBUT, loading that project into the latest ClockBuilder Pro v2.37 [2019-09-22] has issues :(
I can no longer enter 26MHz in the Menus, but the project file appears to remember the 26MHz from before - but new projects are broken.
Fix:: Please restore the ability to select ANY value from nominal 25~27MHz
Smarter would be to allow 24.9975MHz ~ 27.0027MHz entry, to include 100ppm crystal offsets in the forms.
PCIe Clock Jitter Tool can't process this phase noise csv
SI5351B : wrong frequency output
Hi There,
I have an issue with the SI5351B that I can't manage to resolve.
I actually use a 27MHz 8pF xtal to generate a 72MHz clock on out4 and 12.288 on out 6. I use the CBPro tools to generate all the register.
When I set all the register with the procedure described in the datasheet, I do have some clock on the pin but at wrong frequencies : ~96MHz and ~16MHz.
There is a factor 1.3 that come from no where and the frequency does not seems to be very stable.
When I check the status register, it says the plla is unlocked.
Is anybody have an idea to resolve this?
Thanks.
Raphael
PS: here is the init code
void SI5351B_init(void) {
int i;
//Disable Outputs Set CLKx_DIS high; Reg. 3 = 0xFF
SI5351B_set_reg(0x3, 0xFF);
//Powerdown all output drivers Reg. 16, 17, 18, 19, 20, 21, 22, 23 = 0x80
SI5351B_set_reg(16, 0x80);
SI5351B_set_reg(17, 0x80);
SI5351B_set_reg(18, 0x80);
SI5351B_set_reg(19, 0x80);
SI5351B_set_reg(20, 0x80);
SI5351B_set_reg(21, 0x80);
SI5351B_set_reg(22, 0x80);
SI5351B_set_reg(23, 0x80);
//Set interrupt masks
SI5351B_set_reg(0x2, 0xF0);
/* Write new configuration to device using
the contents of the register map
generated by ClockBuilder Desktop. This
step also powers up the output drivers
(Registers 15-92 and 149-170 and 183 */
for (i = 0; i < SI5351B_REVB_REG_CONFIG_NUM_REGS; i++) {
SI5351B_set_reg(si5351b_revb_registers[i].address, si5351b_revb_registers[i].value);
}
//Apply PLLA and PLLB soft reset Reg. 177 = 0xAC
SI5351B_set_reg(177, 0xAC);
while (SI5351B_get_reg(177) & 0xA0); //wait pll reseted
//Enable desired outputs (see Register 3) --register is inverted
SI5351B_set_reg(3, 0xAF); //enable fpga + audio clk, clk 4 - 6
}
There is not clock output using I2C interface to write a pre-programmed SI5338
I used the field programming kit to write directly to the NVM of twenty SI5338. Then I found the configuration file is wrong. I decide to write to registers in RAM through the I2C interface. Here is the question. Seven in the twenty can not be programed successfully. The phenomenon is that there is no clock output.
Any help?
Si5340D EB programming issue DUT/Board mismatch
I believe that I managed to write something wrong to the registers of the chip and have problems to program it with CBPro(2.8.81). I can still program it with an external mcu.
When I start CBPro, I see that evaluation board is detected but Rev Unknown. I open the Default Plan and the EVB GUI. Then I get a message:
DUT/Board mismatch: There is a mismatch between the device present and on the EVB and the type of board. The device is unknown, but a Si5340 board is present (board id is 40d). Please contact Silicon Labs for assistance.
I get this output for the DUT registers
Timestamp Source Message
08:48:44.091 EVB finished Read_DUT_Byte(address=0x0004) => 0xFF
08:48:44.091 EVB Starting Read_DUT_Byte(address=0x0003)
08:48:44.095 EVB finished Read_DUT_Byte(address=0x0003) => 0xFF
08:48:44.099 EVB Starting Read_DUT_Byte(address=0x0004)
08:48:44.104 EVB finished Read_DUT_Byte(address=0x0004) => 0xFF
08:48:44.105 EVB Starting Read_DUT_Byte(address=0x0000)
08:48:44.108 EVB finished Read_DUT_Byte(address=0x0000) => 0xFF
08:48:44.109 EVB Starting Read_DUT_Byte(address=0x0005)
08:48:44.112 EVB finished Read_DUT_Byte(address=0x0005) => 0xFF
08:48:44.112 EVB Starting Read_DUT_Byte(address=0x0009)
08:48:44.116 EVB finished Read_DUT_Byte(address=0x0009) => 0xFF
08:48:44.116 EVB Starting Read_DUT_Byte(address=0x000A)
08:48:44.129 EVB finished Read_DUT_Byte(address=0x000A) => 0xFF
08:48:44.132 EVB Starting Read_DUT_Byte(address=0x0000)
08:48:44.140 EVB finished Read_DUT_Byte(address=0x0000) => 0xFF
08:48:44.140 EVB Starting Read_DUT_Byte(address=0x027D)
08:48:44.144 EVB finished Read_DUT_Byte(address=0x027D) => 0xFF
08:48:44.144 EVB Starting Read_DUT_Byte(address=0x027E)
08:48:44.149 EVB finished Read_DUT_Byte(address=0x027E) => 0xFF
08:48:44.150 EVB Starting Read_DUT_Byte(address=0x026B)
08:48:44.155 EVB finished Read_DUT_Byte(address=0x026B) => 0xFF
08:48:44.155 EVB Starting Read_DUT_Byte(address=0x026C)
08:48:44.160 EVB finished Read_DUT_Byte(address=0x026C) => 0xFF
08:48:44.160 EVB Starting Read_DUT_Byte(address=0x026D)
08:48:44.165 EVB finished Read_DUT_Byte(address=0x026D) => 0xFF
08:48:44.165 EVB Starting Read_DUT_Byte(address=0x026E)
08:48:44.170 EVB finished Read_DUT_Byte(address=0x026E) => 0xFF
08:48:44.170 EVB Starting Read_DUT_Byte(address=0x026F)
08:48:44.175 EVB finished Read_DUT_Byte(address=0x026F) => 0xFF
08:48:44.175 EVB Starting Read_DUT_Byte(address=0x0270)
08:48:44.180 EVB finished Read_DUT_Byte(address=0x0270) => 0xFF
08:48:44.180 EVB Starting Read_DUT_Byte(address=0x0271)
08:48:44.185 EVB finished Read_DUT_Byte(address=0x0271) => 0xFF
08:48:44.185 EVB Starting Read_DUT_Byte(address=0x0272)
08:48:44.195 EVB finished Read_DUT_Byte(address=0x0272) => 0xFF
08:48:44.195 EVB Starting Read_DUT_Byte(address=0x0278)
08:48:44.201 EVB finished Read_DUT_Byte(address=0x0278) => 0xFF
08:48:44.201 EVB Starting Read_DUT_Byte(address=0x0279)
08:48:44.206 EVB finished Read_DUT_Byte(address=0x0279) => 0xFF
08:48:44.206 EVB Starting Read_DUT_Byte(address=0x027A)
08:48:44.210 EVB finished Read_DUT_Byte(address=0x027A) => 0xFF
08:48:44.211 EVB Starting Read_DUT_Byte(address=0x027B)
08:48:44.215 EVB finished Read_DUT_Byte(address=0x027B) => 0xFF
08:48:44.215 EVB Starting Read_DUT_Byte(address=0x027C)
08:48:44.220 EVB finished Read_DUT_Byte(address=0x027C) => 0xFF
08:48:44.224 EVB Starting Read_DUT_Byte(address=0x0006)
08:48:44.228 EVB finished Read_DUT_Byte(address=0x0006) => 0xFF
08:48:44.228 EVB Starting Read_DUT_Byte(address=0x0007)
08:48:44.233 EVB finished Read_DUT_Byte(address=0x0007) => 0xFF
08:48:44.233 EVB Starting Read_DUT_Byte(address=0x0008)
08:48:44.238 EVB finished Read_DUT_Byte(address=0x0008) => 0xFF
Si5340D EB clocks stability
I am evaluation the Si5340 which we intend to use for audio as well as driving a dsp clock. I have noticed that when I make a frequency change to, for example OUT2, then I notice that the clock ouput on OUT0 is affected at the instance of frequency change. I am worried that such a glitch will stop the DSP or other processors that are receiving their clocks from the other Si5340 outputs. Am I doing something wrong when I do any frequency updates or is this expected behavior?
I control Si5340 using i2c and the header files that are generated from CBPro (2.28.1).
Thank's
Alexander