I am trying to build an enclosure for this board. I have looked at the user manual and cannot find dimensions for the mounting holes and board. Is there anywhere where I can find this information out?
I am using the Si5327 evaluation board. Board came without the external power but I set DUT_PWR and 3.3V to 3.3V and things seem to work.
DSPLLsim can generate frequency plans and talk to the board.
When using CKIN1 and a frequency plan with a 1:1 ratio for frequencies in the range 200kHz-1MHz it looks like CKOUT1 locks Ok (although the LOL LED remains red).
However, I can't get the system to lock for frequency plans with 1:1 ratio at CKIN1 freqs of 100kHz or below (happens both with DC or AC coupled inputs).
Clocks which are marked in same colored circles are same in values. I want to share the o/p of a single clock_out_port to both the FPGAs.
How should I analyse the possibility of doing this such that clocks are not loaded? What parameters/specifications should I check in datasheet of Si5341?
Have managed to set-up i2c communication between an i2s master and the evaluation board. Can read and write to/from registers, but I don't get any clock signals from OUT0..3. I program the si5340 chip with an unaltered header file produced by CBPro (2.28.1), Si5340-RevD-5340EVB1-Registers.h. I have a 300ms pause after the end of the configuration preamble. I have also verified that all configuration registers have correct values by reading the reg values after programming has finished. It seems that it's not possible to verify the pre- and post-amble regs - correct?
The board seems to be ok, I get the clock signals when I program the board with CBPro.
What am I doing wrong?
Update:
Connected the field programmer, CBPROG-DONGLE, and successfully downloaded the Si5340 EB sample project. Still no clocks signals. Also tested to write the same project using 4-wire SPI. However, it failed during validation - TOOL_VERSION should be 0x0 but read out 0xFFFFFF. It also says that I should check RST/connectivity/power.
I'm using the Si5340-EB REV 3 evaluation board and are trying to connect to the Si5340 using I2C. However, I have forgot something since I don't get any response back from Si5340. My setup is a Raspberry acting as I2C master and is controlling other I2C slaves on the bus. On the the dev board I have removed all the jumpers on J17 and also removed the jumper on J1, as described in the user guide to 5340-D-EVB. Connected SDA on J17:4 and SCLK on J17:8. I'm using device address 0x74, since register 0x000B is 0x74 in the register file produced by ClockBuilder (why does it say board address 40d in the EVB schamtic, page 2?). My logic analyzer shows that the master is sending a write command to 0x74 (to set the page address) but does not receive an ACK, so there it stops. I2C speed is 100kHz. (Does not matter if I remove the other slaves from the bus). All the time the Si5340 is running as I can see the clock output OUT0 on the scope.
I need some help with the Si53159 Fanout Buffer.
Designing a PCIe add-in Board I want to use this new clock buffer. Before this Low-Power HCSL Si53159 chip we used usual HCSL clock buffers, which needed extra series resistors (33 Ohm to minimize Ringing) and a Termination resistor (50 Ohm while the clock line has 50 Ohm).
Can you please confirm, that using this LP-HCSL Si53159 clock buffer has series resistor (33 Ohm) and the Termination (50 Ohm) inside of the chip?
From the Datasheet for the chip , EvBoard doc, AN781 it is not clear: are theese resistors (33 Ohm and 50 Ohm) already in the case? Or do I need to add external 33 Ohm resistor in series?
The second question is: can I connect the 100MHz clock output from Si53159 to the clock Input of the Intel I210 chip directly without AC coupling and series/Termination (see the schematic attached)?
For some of our projects we are evaluating the Si534x family as jitter cleaners and/or clock generators. In some of our setups it is necessary that certain clock signals are present upon power-up. With this in mind we followed the field-programming instructions to program (the NVM of) an Si5344-D-EVB evaluation board such that it produces the correct output frequencies (and formats) upon power-up. This all works fine, but to our surprise we found that upon power-up the VDO0-3 regulators are not enabled (presumably this should be done by the MCU). Hence still no clock signals at the outputs.
Does anybody know of a way to obtain an MCU firmware version that correctly enables all voltage regulators on the board upon power-up?
Hello! In the datasheet is the phrase (page 1):"Supports static phase offset ".What does it mean? Can I using SI5351 for generation two phase-shifted (0 and 90 degrees) signals?The frequency is roughly 130MHz.Are here any initialization libraries for STM32? Thanks for answers!
Hi,I have encoutered a problem when using Si5319 to generate a clock.I provide a input clock to Si5319 which ranges from 62.5MHz to 500MHz,I want the Si5319 to generate a output clock exactly equal to my input clock,which means N2/(N1*N3) should exactly equal 1,I used DSPLLsim to generate the data to configure all reg.
Now the problem is :When my input clock frequency higher than 200MHz,the output clock frequency is exactly equal to input clock's.However ,when the input clock frequency lower than 200MHz,for example when input clock frequency is 179.9999MHz,I set N1_HS = 7,NC1_LS = 4,N31 = 60000,N2_HS = 10,N2_LS = 168000 according
to DSPLLsim,the actual output clock frequency is 179.9989MHz,not exactly equal to input clock,and the clock precision is lowered,I tried to ajust the value of N31 and N2_LS but to no effect.What should I do to solve this problem?
I'm working on a board which includes both an FPGA and a Si5340, production does not want to have to program both devices, so I need a way to configure the Si5340 from the FPGA. Adding an I2C core etc is easy, but I need to know how much memory a configuration takes. The FPGA will have some memory left over in its EEPROM but I need to know if that will be enough.
Then of course I need some way to get the configuration data from CBP, what files to read and figure out how to get that into data I can load in the FPGA memory and how to get that into I2C commands for sending to the Si5340.
I tried loading the phase noise data (SSC_OFF_phase_noise.csv) provided with the sample data si5332 Low JItter Clock Generator, which available on the Si Labs webpage. Unfortunately I get an error saying that the format is wrong. Is this maybe an old example and the format has changed in the new version? However the .csv file looks compliant to the file format description. I also tried removing the header, without success.
Forum
si5xx-prog-evb mounting holes dimensions
I am trying to build an enclosure for this board. I have looked at the user manual and cannot find dimensions for the mounting holes and board. Is there anywhere where I can find this information out?
Thanks
Si5327 evaluation board fails to lock < 200kHz?
I am using the Si5327 evaluation board. Board came without the external power but I set DUT_PWR and 3.3V to 3.3V and things seem to work.
DSPLLsim can generate frequency plans and talk to the board.
When using CKIN1 and a frequency plan with a 1:1 ratio for frequencies in the range 200kHz-1MHz it looks like CKOUT1 locks Ok (although the LOL LED remains red).
However, I can't get the system to lock for frequency plans with 1:1 ratio at CKIN1 freqs of 100kHz or below (happens both with DC or AC coupled inputs).
What am I doing wrong?
Thank you!
--
Dario
Si5341 clock sharing
Dear All,
Please refer to the attached slide.
Clocks which are marked in same colored circles are same in values. I want to share the o/p of a single clock_out_port to both the FPGAs.
How should I analyse the possibility of doing this such that clocks are not loaded? What parameters/specifications should I check in datasheet of Si5341?
Si5335 - unused P1-P6 termination
Hi,
I am not using Pin P6 of Si5335B. How should it be terminated?
Thanks
Si5335 - P/N/R meaning
I have created a Si5335B Clock profile (attached doc).
What are P,N and R dividers mentioned in the doc?
I don't see much info about them in datasheet.
3 SI5351 from a single reference crystal - Crosstalk
Hi,
I'm a homebrewer (radio ham) and am looking to see if I can use 2 or 3 SI5351 ICs to generate separate clock outputs instead of using just the one.
I'm trying to reduce the effects of crosstalk - see https://nt7s.com/tag/crosstalk/
Are there any published Application notes or ideas that learned folk from this forum can share?
Thank you for your time.
Ravi
Si5340-EB evaluation board - no clock signals
Have managed to set-up i2c communication between an i2s master and the evaluation board. Can read and write to/from registers, but I don't get any clock signals from OUT0..3. I program the si5340 chip with an unaltered header file produced by CBPro (2.28.1), Si5340-RevD-5340EVB1-Registers.h. I have a 300ms pause after the end of the configuration preamble. I have also verified that all configuration registers have correct values by reading the reg values after programming has finished. It seems that it's not possible to verify the pre- and post-amble regs - correct?
The board seems to be ok, I get the clock signals when I program the board with CBPro.
What am I doing wrong?
Update:
Connected the field programmer, CBPROG-DONGLE, and successfully downloaded the Si5340 EB sample project. Still no clocks signals. Also tested to write the same project using 4-wire SPI. However, it failed during validation - TOOL_VERSION should be 0x0 but read out 0xFFFFFF. It also says that I should check RST/connectivity/power.
/AJ
I2C communication problem with Si5340-EB evaluation board
I'm using the Si5340-EB REV 3 evaluation board and are trying to connect to the Si5340 using I2C. However, I have forgot something since I don't get any response back from Si5340. My setup is a Raspberry acting as I2C master and is controlling other I2C slaves on the bus. On the the dev board I have removed all the jumpers on J17 and also removed the jumper on J1, as described in the user guide to 5340-D-EVB. Connected SDA on J17:4 and SCLK on J17:8. I'm using device address 0x74, since register 0x000B is 0x74 in the register file produced by ClockBuilder (why does it say board address 40d in the EVB schamtic, page 2?). My logic analyzer shows that the master is sending a write command to 0x74 (to set the page address) but does not receive an ACK, so there it stops. I2C speed is 100kHz. (Does not matter if I remove the other slaves from the bus). All the time the Si5340 is running as I can see the clock output OUT0 on the scope.
Thank's Alexander
(images of bus analyzer and board i2c connections, https://photos.app.goo.gl/iHcJZdqprWWUdiaKA)
Si53159 connecting directly to Intel I210
Hallo,
I need some help with the Si53159 Fanout Buffer.
Designing a PCIe add-in Board I want to use this new clock buffer. Before this Low-Power HCSL Si53159 chip we used usual HCSL clock buffers, which needed extra series resistors (33 Ohm to minimize Ringing) and a Termination resistor (50 Ohm while the clock line has 50 Ohm).
Can you please confirm, that using this LP-HCSL Si53159 clock buffer has series resistor (33 Ohm) and the Termination (50 Ohm) inside of the chip?
From the Datasheet for the chip , EvBoard doc, AN781 it is not clear: are theese resistors (33 Ohm and 50 Ohm) already in the case? Or do I need to add external 33 Ohm resistor in series?
The second question is: can I connect the 100MHz clock output from Si53159 to the clock Input of the Intel I210 chip directly without AC coupling and series/Termination (see the schematic attached)?
Thank you for your answers.
How to enable VDDO0/1/2/3 on Si5344 dev board upon power-up?
Dear all,
For some of our projects we are evaluating the Si534x family as jitter cleaners and/or clock generators. In some of our setups it is necessary that certain clock signals are present upon power-up. With this in mind we followed the field-programming instructions to program (the NVM of) an Si5344-D-EVB evaluation board such that it produces the correct output frequencies (and formats) upon power-up. This all works fine, but to our surprise we found that upon power-up the VDO0-3 regulators are not enabled (presumably this should be done by the MCU). Hence still no clock signals at the outputs.
Does anybody know of a way to obtain an MCU firmware version that correctly enables all voltage regulators on the board upon power-up?
Best regards,
Jeroen Hegeman
Two bytes register address for si5332 rev C
I just generated c header file for si5332 using ClockBuilder Pro v2.27 for si5332-GMI-RevC, the register address is 2 bytes:
0x4024, 0x02
The MSB is all 0x40, my question is the register address for i2c should be only one byte?
Thanks
"IQ" signals using SI5351
The output frequency of Si5319 is not exactly equal to input when N2/(N1*N3)=1
Hi,I have encoutered a problem when using Si5319 to generate a clock.I provide a input clock to Si5319 which ranges from 62.5MHz to 500MHz,I want the Si5319 to generate a output clock exactly equal to my input clock,which means N2/(N1*N3) should exactly equal 1,I used DSPLLsim to generate the data to configure all reg.
Now the problem is :When my input clock frequency higher than 200MHz,the output clock frequency is exactly equal to input clock's.However ,when the input clock frequency lower than 200MHz,for example when input clock frequency is 179.9999MHz,I set N1_HS = 7,NC1_LS = 4,N31 = 60000,N2_HS = 10,N2_LS = 168000 according
to DSPLLsim,the actual output clock frequency is 179.9989MHz,not exactly equal to input clock,and the clock precision is lowered,I tried to ajust the value of N31 and N2_LS but to no effect.What should I do to solve this problem?
Configure Si5340 from FPGA
I'm working on a board which includes both an FPGA and a Si5340, production does not want to have to program both devices, so I need a way to configure the Si5340 from the FPGA. Adding an I2C core etc is easy, but I need to know how much memory a configuration takes. The FPGA will have some memory left over in its EEPROM but I need to know if that will be enough.
Then of course I need some way to get the configuration data from CBP, what files to read and figure out how to get that into data I can load in the FPGA memory and how to get that into I2C commands for sending to the Si5340.
Thanks,
John S.
PCIe Clock Jitter Tool - Error loading phase noise data
Hi everyone,
I tried loading the phase noise data (SSC_OFF_phase_noise.csv) provided with the sample data si5332 Low JItter Clock Generator, which available on the Si Labs webpage. Unfortunately I get an error saying that the format is wrong. Is this maybe an old example and the format has changed in the new version? However the .csv file looks compliant to the file format description. I also tried removing the header, without success.
Is this maybe a software bug?