In Si5330x Data Sheet, chapter 2.2 Internal Input Bias Resistors, there has one sentence:
The clock input should not be actively driven when power is not applied to the device.
My question is how important is the input order? Can I power Si5330x and the input clock at about the same time or a few minutes late?
I bought Si53208EVB to learn how to program the 53204. The 3-pin I2C header is available but no document what hardware can be used to these pins.
Is there any GUI software supporting this EVB? Does the signals support 3.3V level? The signals are pulled up by a 1.8V supply as shown in the reference design. Thanks.
For test purposes, use registers 0x135 ... 0x139 (scratch).
Nothing more than simply writing and reading these registers to test the I2C interface.
We experience errors although the device can be initialized perfectly well (the controller works as it should).
It seems not all bits in the scratch registers can be modified in contrary to what is stated in the datasheet ("Si5341, Si5340 Rev D Family Reference Manual".
Missinterpreting on our side or error in the data sheet?
Thanks for any answer.
In applications where not all frequencies are known ahead of time (neither for free-run nor for jitter filtering modes), according to the CBPro Tools & Support In-System Programming doc the Update configuration (DIY) flow should be used. Suppose the task is to write a Linux driver for the Si5342.
If that is too complex, I guess the second best approach is trying to cover common frequencies and use the full configuration or FOTF approaches to calculate look-up tables for each.
How should one go about this?
I am working on a prototype design that uses the Si5351A clock generator.
When I power the board up, the Si5351 outputs a 22.7 MHz clock on OUT0, nothing out on CLK1 or CLK2.
The part does not respond to any I2C accesses. The number on the part is 5351 B2B9 425. I have also tried a part with number 5351 A8GD 507.
I know my I2C driver works fine because I have tested it with a Si5351 breakout board. Is it possible that these parts are factory programmed and have a different I2C address ?
I'm running them at 3.3V with 3.3V I2C signaling. The 25 MHz oscillator is working properly. I have never seen a part power up with any outputs active.
I bought them from distribution, namely Mouser. Their Silicon Labs part number is SI5351A-B02075-GT.
Does the skew control function that was available in die rev A still work in rev b and newer parts?
I have a die rev B part that I am unable to change the output to output skew and it does not match what was programmed via clock builder.
I'd like to use the Si5341 IN_SEL to switch between two clock sources XA/AB <-> IN0 in the scenario where IN0 is missing.
The two reference clocks will be the same frequency but are not phase locked.
What should we expect to see on the Si5341 output during this transition?
Now i testing for Si5351A[3 output] Clock generator and i want to control it directly with I2C
I am experimenting with a code that output only CLK0 with a test, but the desired output is not coming out!
Please let me know to advice, if there are any settings that need to be added or changed
(OUTPUT CLK 0)
Multisynth output Frequency(MHz)=87.5
Multisynth Divider =8
R Divider =1
PLL Source = PLLA
1. When Fanout(Register 187) setting is disabled, the desired output does not come out and CLK0 pin status is low.
2. When Fanout(Register 187) setting is enabled, only XTAL frequency of 25MHz is output
● Setup code
/* SI5351A Output disable, powerdown */
I2C_Write(0xC0, 0x03, 0xFF); // CLKOutput Disable
/* SI5351A clk2-0_Output configuration */
I2C_Write(0xC0, 0x10, 0x43); // CLK0 use PLLA,integer mode, Drive : 8ma ,Register 16
I2C_Write(0xC0, 0x11, 0x43); // CLK1 use PLLA,integer mode, Drive : 8ma, Register 17
I2C_Write(0xC0, 0x12, 0x43); // CLK2 use PLLA,integer mode, Drive : 8ma, Register 18
/* SI5351A PLLA setting */
I2C_Write(0xC0, 0x1A, 0x00); // MSNA_P3[15:8], Register 26
I2C_Write(0xC0, 0x1B, 0x00); // MSNA_P3[7:0], Register 27
I2C_Write(0xC0, 0x1C, 0x00); // MSNA_P1[17:16], Register 28
I2C_Write(0xC0, 0x1D, 0x00); // MSNA_P1[15:8], Register 29
I2C_Write(0xC0, 0x1E, 0x1C); // MSNA_P1[7:0] 8h`0x1c integer : 28 , 25*28 = 700MHz = PLLA ,Register 30
I2C_Write(0xC0, 0x1F, 0x00); // MSNA_P3[19:16],MSNA_P2[19:16] , Register 31
I2C_Write(0xC0, 0x20, 0x00); // MSNA_P2[15:8], Register 32
I2C_Write(0xC0, 0x21, 0x00); // MSNA_P2[7:0], Register 33
/* SI5351A Multisynth0(clk 0) setting */
I2C_Write(0xC0, 0x2A, 0x00); // MS0_P3[15:8], Register 42
I2C_Write(0xC0, 0x2B, 0x00); // MS0_P3[7:0], Register 43
I2C_Write(0xC0, 0x2C, 0x00); // R0_DIV:000 , MS0_DIVBY4:00, MS0_P1[17:16], Register 44
I2C_Write(0xC0, 0x2D, 0x00); // MS0_P1[15:8], Register 45
I2C_Write(0xC0, 0x2E, 0x08); // MS0_P1[7:0], Register 46 PLLA=700MHz/Div(8),CLK0 output=87.5MHz
I2C_Write(0xC0, 0x2F, 0x00); // MS0_P3[19:16], MS0_P2[19:16], Register 47
I2C_Write(0xC0, 0x30, 0x00); // MS0_P2[15:8], Register 48
I2C_Write(0xC0, 0x31, 0x00); // MS0_P2[7:0], Register 49
/* SI5351A PLL reset setting */
I2C_Write(0xC0, 0xB1, 0xAC); // PLLA, PLLB Reset, Register 177
/* SI5351A Cystal internal load capacitance setting */
I2C_Write(0xC0, 0xB3, 0xD2); // 8b, Register 183
/* SI5351A Fanout Enable/Disable setting */
I2C_Write(0xC0, 0xBB, 0xD0); // eable clock output multiplexers , Register 187
/* SI5351A output enable setting */
I2C_Write(0xC0, 0x03, 0x00); // clk7-0 output enable, Register 3
Si5348 Revision D Reference Manual, Rev. 1.4, page 43, chapter 6.5 Output Enable/Disable, 3rd sentence:
"The output enable pins can be mapped to any of the outputs (OUTx) through register configuration."
What is the address of this register, what is the description of it? I didn't find it yet.
1. what is the purpose of frequency select pin (FS = 0, 1) in 516FHA000132AAG voltage controlled Oscillator , is it for fine tuning ? .
2. is the output frequency within 100khz to 250mhz proportional to controlling voltage (Vc) ?
In Si5351 App note AN619, Rev .7, page 3, the following equation is presented to calculate the PLL feedback MS values:
MSNx_P1[17:0] = 128 x a + Floor (128 b /c) - 512
Can someone please explain how this equation is derived?
I have read in AN619 on p. 60, section "Register 177. PLL Reset", that you can reset PLL A and B. Unfortunally, the behaviour is not documented. My questions:
We got Si5395 Evaluation Board, then try to check it functional or not, so we prepare Signal Generator "R&S SMJ100A" generated 1 MHz Sine wave, check it by Oscilloscope,
Oscilloscope display correct sine wave , frequency measured result shows: 1 MHz. So , connect Signal Generator output to Si5395 Evaluation Board Clock Input "IN0",
configure Clock Builder Pro output "OUT9A", press button "write design to EVB" and "Open EVB GUI" , connect "OUT9A" to Oscilloscope, it shows square wave
on Oscilloscope, stop Signal Generator , but Oscilloscope shows square wave continuous. Does it missing steps or some suggestion for us?
(1). Does Si5395 Evaluation Board support sine wave input, then output sine wave? how about jitter clean capability?
(2). Attach Si5395 Evaluation Board configuration file, would you check it to find out the problems? Thanks.
I guess, I have found some typos in the documentation "AN619" for the SI5351.
I hope, that help!