I am currently using the Phase INC/DEC function with the Si5338.
1) The datasheet says that the accuracy of phase steps is "20ps" MAX.
However I have measured the repeatability of these phase steps to be <4ps RMS. Also, the granularity is more of the order of 3ps.
2) And for example on this post, we have an example of how to set up a 20ps phase step size
(which is questionable if the phase step accuracy is 20ps. You would not want to have 0ps steps when you programmed 20ps. )
-> So my question is: why is the quoted accuracy of 20 ps while it seems to perform much better? what is the limitation (temperature effects, ageing, ... ? )? Is there a Silabs alternative which would achieve 3ps?
We have a board with Si5347D-D on it.
It works fine, but we haven't find how to force one (or all) PLLs to go into freerun mode by registers access?
NOT holdover, 100% freerun with frequencies sourced from external XO.
This is required when input have some frequency and it can be locked, but the source of frequency is wrong and should be replaced by XO' sourced frequency.
We have SPI access to Si5347D chip, so best way is to find what registers should be changed to give us what we need.
Thank you in advance for any help.
We are using si5342, the input frequency is determined by incoming data, and so is the output frequency.
I prefer not to use ClockBuilder Pro and create all the options - since there are many.
Is there a way to calculate all the registers' values and set them on run time? We don't mind doing a soft reset or other procedure to make the effect.
On the SI56361 datasheet electrical specification,
Table 3.2 indicates :
-LVCMOS Input High Voltage VIH VDD x 0.7 V
-LVCMOS Input Low Voltage VIL VDD x 0.3 V
Meaning that clock level shall be under VDD x 0.3 V (for low level), and over VDD x 0.7 V for (high level). So more than 1.32Vpp when VDD is 3.3V.
Table 3.6, additive jitter is given for Vin Peak-to-Peak amplitude at 0.15 and 0.5 V.
Is there a mistake or does the circuit really operate with such low input level voltage?
In such case, is Clk in internaly polarized ? Can we connect the inputs with capacitors ?
Thanks for your help
I have an application where I need to clean a jittery clock signal. A prototype with the 5344 works well for a few test frequencies, however the final product needs to accept inputs from a range of frequencies, for which is not feasible to generate all the registers from ClockBuilder Pro.
I think I see how to program the registers I need, with the exception of BW_PLL, for which the manual just says "The loop BW values are calculated by ClockBuilder Pro and are written into these registers". Is there any documentation available for how to calculate BW_PLL?
This Community thread is for feedback on the new Silicon Labs PCIe Clock Jitter Tool. The tool was recently announced and is available as a free download here:
We are very excited for people to try it out! Please let us know any feedback or suggestions that should be addressed in future updates.
Silicon Labs Timing Support Engineers
I'm running two outputs of the SI5382A at 2.5GHz, Clock Builder Pro says these will be configured as High Speed Differential, but neither the data sheet nor the reference model defines what the output type is and how to properly terminate them.
In order to use this chip on a board I need to know how these outputs should be terminated.
We are designing a PCB using Si5345. On page 32 in "Si5345/44/42 Rev D Data Sheet Rev1.2", there is a description that "Ref clock rise time must be <200 ps."
Does "Ref clock" mean the input clock for IN0-3 pin or the external reference clock for XA/XB pin? If "Ref clock" means the input clock, we have to redesign the PCB.
Hi, I have written a library for the Arduino that allows control of nearly all of the functions of the Si5351A (without having to use ClockBuilder), however there is one command that I cannot get to work correctly, and that is setting the initial phase.
Allow me to describe my observations. If I take CLK0 and CLK1 and set them to be referenced to PLLA and to be set to the exact same frequency, they will be initialized at a seemingly random phase in reference to each other. However, when I set the CLK0 and CLK1 phase registers to the same phase value (I chose 0 and other values), I observe the exact same behaviors. To illustrate what I see, here are some screen captures from my oscilloscope showing the random initial phase values upon startup. Each time, I just cycled power between screen captures.
AN619 implies, but does not outright state, that the phase registers should be set before setting the MS registers, so I initially did that, but to no avail. I also tried setting the phase registers after setting the MS registers, but that also did not help. I assume there is some specific procedure for setting the phase registers that I am missing, but I cannot find it in AN619. Any help I can get in this area would be greatly appreciated.
Having this capability will allow us to do some neat things with the SI5351, such as using it as a quadrature local oscillator for SDR applications and doing phase modulation like PSK.
I'm testing the Si5326 for regenerating a noisy 12 KHz clock. I have read previous notes that the input to output skew is nondeterministic on the Si5326, but in my testing the variation in skew is very small relative to my clock period and I think is probably not relevant for my application. However, I am having trouble zeroing the phase delay.
Looking at "188.8.131.52. Unlimited Coarse Skew Adjustment (Si5326, Si5368)" in the reference manual, there is a procedure outlined that iteratively adjusts the CLAT and INCDEC pins to shift the phase delay by 25ns ever 15 or so seconds. While this does work, adjusting a 12 kHz clock at this rate of tuning takes forever due to the extremely long time to for the CLAT changes to lock and the small adjustment per lock, and of course the results are lost when the device powers down and the entire lengthy process must be repeated.
Is there anything I can do to more rapidly adjust the phase delay? I do not require extremely low phase offset between the inputs to outputs.
we are using thousands of Si5351 for different products and have issues to get our custom programmed parts in time for upcoming production lots, which is a big concern for us, obviously.
Is there a way to program unprogrammed parts (which would be better available) ourselves or by an external programming service?
Another option we are considering is to use a different pre-programmed part (some of them appear to be available at various distributors) and reconfigure them accordingly after startup via I²C. But is there a way to find out the programming of these parts as we have to make sure that our board at least boots with this different configuration (it is also the main clock of our system)?