Hi Hary / Tim ,
about the BW for messuring:
you said that need at least 5 Ghz,
it's seems so high, the carrier is just 100 Mhz.
what is the explanation with this requirement ?
I've build a small clock generator module around Si5351A-B-GMR (QFN-20 package, top marking Si5351 B00E09 1608), that makes all 8 clock outputs available. But I am having a problem with generating correct frequencies on outputs CLK0 thru CLK5.
I can program the chip over I2C just fine, but the output frequencies on CLK0 thru CLK5 are all roughly 1.5X higher than they should be. BUT Output frequencies (integer div) on CLK6 and CLK7 are correct. I have also mirrored the xtal oscilator (X0) to CLK1 to check the oscillator frequency, and it is running at a solid 25.000 MHz. (I am using a 25 MHz Abracon ABM8G-25.000MHZ-B4Y-T crystal. All components were purchased from Mouser.)
My original prototyping work was done with the Adafruit Si5351A Clock Generator Breakout Board, which has an Si5351A-B-GT (MSOP-10 package, top marking 5351 B600 507). This board only had 3 outputs, but it generates the correct frequencies. I thought it would be a simple matter to substitute Si5351A-B-GM, but the lower 6 outputs are not generating the same frequencies as I can get on the Si5351A-B-GT with the same register settings.
For what it's worth, I was originally programming this from an Arduino using Adafruit's own Si5351 library (which only supports the first 3 outputs). Wrong frequencies. I then switched to EtherKit/Si5351Arduino (which supports all 8 outputs), but I still get the wrong frequencies on CLK0 thru CLK5. I'm definitely initializing the libraries for a 25 MHz crystal, too, unless there is some bug in the library code that affects Si5351A-B-GM but not Si5351A-B-GT.
THIS SEEMS VERY STRANGE.
Is there something different about the multisynth architecture or programming between Si5351A-B-GT and Si5351A-B-GM? Hopefully this is something I can easily fix in code.
I decided to try using different combinations of PLLA and PLLB and the various multisynths/outputs. This is what I discovered:
Both PLLs are supposedly programmed for 800 MHz. PLLB appears to be very stable. PLLA appears to be relatively unstable, producing ultimate output frequencies that vary by ±0.1%.
When using PLLB, CLK0 thru CLK5 produce frequencies that are that are approximately 1.1X higher than what they should be. CLK6 and CLK7 produce correct frequencies.
When using PLLA, CLK0 thru CLK5 produce frequencies that are that are approximately 1.5X higher than what they should be, and unstable. CLK6 and CLK7 produce frequencies that are that are approximately 1.355X higher than what they should be.
Mirroring the crystal oscillator to a CLK pin produces the correct, stable, 25.000 MHz frequency output on that pin in all cases.
My conclusion is that there is something wrong with the multisynth math on MS0 thru MS5, and something very wrong with PLLA.
We need tape and reel packaging spec for part# Si53301-B-GMR, can you pls advise. Thanks.
Now,I have two module must synchornized to a 50 MHz clock source,just like below:
The sinwave is ocassionaly removed one cycle leaved high level , and two high level interval lager than 1s.
then this signal will be recoverd by two Si5317, and my question is :the two recoverd sigal is same,if not same,what the different?
How to write the Hex File Generated From CBpro in Non Volatile Flash Memory with i2c to our Customized PCB without using any Programmer??
Plz help ???
hi, I'm a student and want to use the SI5324 to produce a clock which is 50Mhz, the input is also 50Mhz, this is my frequency plan:
I'm wondering if the SI5338 would accept a clipped sine input from a TCXO on the pin IN3, or we should go through some kind of CMOS signal translator??