When I config the SI5383 Eva-board through ClockBuilder Pro, the tool report a error ,just as the image below;
if anyone has seen the error before and how to fix it?
I'm having issues to understand how the drift in the input frequencies propagates to the output frequencies. Drift that can come either from the XAXB pins or input pins.
For example let's say I have a 50MHz crystal +50ppm and a input 25MHz + 50ppm, if I create a X MHz output, how can I know how imperfect the output frequency will be ?
I have got a registers.h file from CBPro 2.25 and I want to use it for configuration. I read in the file and wrote the registers via I2C as it. A short break (300msec) after the preamble is also included. But the outputs are still zero, no reaction. If I write the same project register file via CBPro and SPI interface (evaluation board) it works perfectly.
So what is the difference between writing the registers with the CBPro tool via SPI and on the other side over I2C interface by my own ?
I want to programme the SI5345 which has been mounted on the board. Now there is Virtex-6 FPGA and my target is to write the register file into the IC using SDK (microblaze). I have generated the register file through ClockBuilderPro. Can you tell me what should be the approach to write into IC using microblaze processor.
The SI5324 has two inputs and two ouputs, so could I use the it to perform a jitter attenuation for two input clocks at the same time (both active at the same time) and get the two ouputs also at the same time ?
Thanks in advance.
I need to generate a low-jitter(<1.5 rms) LVPECL clock,from a clock genenrated by ADF4351(typical phase noise is -83dbc/Hz@10kHz),what kind of jitter I can expect on the output clock based on the above data?Will it meet my requirement?
How to get access to the software of calculating the Si5319's register value ?
Hardware: Xilinx ZC706 Evaluation board
I have programmed Si5324 using steps outlined by forum post:
"Can Si5324 be used as clock generator?", link: https://www.silabs.com/community/timing/forum.topic.html/can_si5324_be_useda-jSSl
I have attached the recommended settings file from answer to that forum post.
Firstly I sent reset to Si524. And I2C programming went smoothly, Si5324 I2C slave acknowledged each write.
After programming, I did not get any output at CKOUT1 or CKOUT2. I also set Reg 0 to Bypass and CKOUT_ALWAYS_ON. Still no output.
I measured INT_C1B and C2B and they are both high, suggesting that XTAL input is not present. However, I have verified that 114MHz XTAL input is indeed present.
Pls help to suggest steps to debug the problem. Si5324 schematic on ZC706 is attached
What's the impact on the common mode voltage level at receiver end if SI5341A is configure to outputs a LVPECL @ 2.5V supply, but its VDDO is tie to 1.8V supply instead of 2.5V? The circuit is AC coupled with 0.1uF capacitor.
We have several 540BAAyyyMxxxBAG oscillators included in our design. We are simulating signal integrity of the design and I don't seen an IBIS mode on the product page of the 540. Can you provide me with a model or point me to the place I can download the model. I was able to download models for other oscillators.
I'm trying to use the ClockBuilder (2.25) with a Si5340 chip, using :
At the end I have one error :"Must define a non-Zero Delay Mode input on DSPLL"
I've tried to search about what would be the meanig of this, but I couldn't find it. I've tried to change input location, frequencies... The only way to remove it is not using the ZDM mode, which is weird. What can I do to solve this ?
Thanks in advance,