I'm testing the Si5326 for regenerating a noisy 12 KHz clock.  I have read previous notes that the input to output skew is nondeterministic on the Si5326, but in my testing the variation in skew is very small relative to my clock period and I think is probably not relevant for my application.  However, I am having trouble zeroing the phase delay. 

Looking at "6.7.1.1. Unlimited Coarse Skew Adjustment (Si5326, Si5368)" in the reference manual, there is a procedure outlined that iteratively adjusts the CLAT and INCDEC pins to shift the phase delay by 25ns ever 15 or so seconds.  While this does work, adjusting a 12 kHz clock at this rate of tuning takes forever due to the extremely long time to for the CLAT changes to lock and the small adjustment per lock, and of course the results are lost when the device powers down and the entire lengthy process must be repeated.  

Is there anything I can do to more rapidly adjust the phase delay?  I do not require extremely low phase offset between the inputs to outputs. 

Hello guys, good morning.
I have already post this message weeks ago, but it didn't receive any answer.
I post again now here, explaining the question better.
My apologies if this will annoy you. Of course this is last time I post this.

I'm using Si5351A for transmitting on 14 MHz frequency. This chip has 3 clocks (CLK0, CLK1 and CLK2).

I would kindly ask you if it is possible to transmit (generate clock signal) at same time on three different frequencies, e.g. 14097000, 14097100 and 14097200 Hz, or anyhow three different frequencies everytime in a range of 200 Hz, no more. Has anyone tried to do this?
Thank you so much for your appreciated help.

Roberto.

Hello,

I am using a Si5341 on my FPGA board. Initially, I had not programmed the NVM on the Si5341 and was using the Linux driver to configure it dynamically. This was working fine. Now, I programmed the NVM with a default setting I would like to have, and the driver can later change this if required. However, after programming the NVM, I see the clock outputs are fine, but the driver is not able to access the chip over I2C any more. I get the error: "Failed to read chip ID". If I try to manually access the I2C from userspace, I get "No such device" error. Is this expected behavior by any chance? Does the IC become inaccessible after NVM programming?...I would hope not!

The weirdest thing is that if I connect the CB Programmer, it continues to recognize the device over I2C at the same address. However, sometimes it has now started throwing I2C errors too. Any ideas what might be wrong here?

Hi:

I am trying to use IN5/6 as reference clock to output 148.5 MHz clock on Si5338.  Based on the flow chart from Si5338 Datasheet. We need to set PLL to use FCL values after read the register map. But if we do that, the PLL will never lock. If we skip that step, it seems that the PLL can lock.

So as showed above, skip the heighted step. I don’t know whether it's ok to do that and whether it will bring in any risks. My configuration code is showed below. Could anyone kindly take a look and give me some suggestion?

int init_TB()
{
    int Status = XST_SUCCESS;
    XIic si5338Iic;
    u8 clear_curr_val;
    u8 clear_new_val;
    u8 curr_chip_val, combined;
    int counter;
    Reg_Data curr;

    Status =  Orbbec_init_iic(IIC_DEVICE_ID);

    /*
    		 * Set the Slave address.
    		 */
    		Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE,
    				IIC_SI5338_ADDRESS);
    		if (Status != XST_SUCCESS) {
    			return XST_FAILURE;
    		}


    		//Disable Outputs: Set OEB_ALL = 1; reg230[4]
    		Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 230, ReadBuffer, 1);
    		//WriteBuffer[1] = ReadBuffer[0] | (1 << 4);
    		WriteBuffer[1] = 0x10;
    		WriteBuffer[0] = 230;
    		Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);


    		//Pause LOL: Set DIS_LOL = 1; reg241[7]
    		Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 241, ReadBuffer, 1);
    		//WriteBuffer[1] = ReadBuffer[0] | (1 << 7);
    		WriteBuffer[1] = 0xE5;
    		WriteBuffer[0] = 241;
    		Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
    		/**/
    		for(counter = 0; counter < NUM_REGS_MAX ; counter++){
				 curr = Reg_Store[counter];
				 if(curr.Reg_Mask != 0x00) {
					 if(curr.Reg_Mask == 0xFF) {
					// do a write transaction only
					// since the mask is all ones
					 ///I2C_ByteWrite(curr.Reg_Addr, curr.Reg_Val);
					 WriteBuffer[0] = curr.Reg_Addr;
					 WriteBuffer[1] = curr.Reg_Val;
					 Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
					  } else {
					//do a read-modify-write
					  ///curr_chip_val = I2C_ByteRead(curr.Reg_Addr);
					  Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, curr.Reg_Addr, ReadBuffer, 1);
					  curr_chip_val = ReadBuffer[0];
					  clear_curr_val = curr_chip_val & ~curr.Reg_Mask;
					  clear_new_val = curr.Reg_Val & curr.Reg_Mask;
					  combined = clear_new_val | clear_curr_val;
					  ///I2C_ByteWrite(curr.Reg_Addr, combined);
					  WriteBuffer[0] = curr.Reg_Addr;
					  WriteBuffer[1] = combined;
					  Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
					  }
				  }
			  }



    		//Validate input clock status
                Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 218, ReadBuffer, 1);
                         xil_printf("5338Reg[218] = %d\r\n", ReadBuffer[0]);

              //Validate input clock status!!!
                         ReadBuffer[1] = (ReadBuffer[0] & (1 << 3));
                         //ReadBuffer[1] = (ReadBuffer[0] & (1 << 2));
           while (ReadBuffer[1] != 0) {
        	   Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 218, ReadBuffer, 1);
        	   ReadBuffer[1] = (ReadBuffer[0] & (1 << 3));
        	   //ReadBuffer[1] = (ReadBuffer[0] & (1 << 2));

           }
           	   //Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 218, ReadBuffer, 1);
              //            xil_printf("5338ReadBuffer[218] = %d\r\n", ReadBuffer[0]);

              //Configure PLL for locking Set FCAL_OVRD_EN = 0; reg49[7]

           WriteBuffer[1] = (ReadBuffer[0] & 0x7F);
			  WriteBuffer[0] = 49;
			  //WriteBuffer[1] = 0x00;
			  Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
			  Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 49, ReadBuffer, 1);
			             xil_printf("5338Reg[49] = %d\r\n", ReadBuffer[0]);

			  //Initiate Locking of PLL Set SOFT_RESET = 1; reg246[1]
			  WriteBuffer[0] = 246;
			  WriteBuffer[1] = 0x02;
			  Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);

			  usleep(25 * 1000);

			  //Restart LOL Set DIS_LOL = 0; reg241[7] Set reg 241 = 0x65
			//Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 241, ReadBuffer, 1);
			//WriteBuffer[1] = ReadBuffer[0] | (0 << 7);
			WriteBuffer[0] = 241;
			WriteBuffer[1] = 0x65;
			Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);

			//Confirm PLL lock status
			Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 218, ReadBuffer, 1);
			//xil_printf("5338ReadBuffer[218] = %d\r\n", ReadBuffer[0]);
			//???
			ReadBuffer[1] = (ReadBuffer[0] & 0x19);
			//ReadBuffer[1] = (ReadBuffer[0] & 0x15);
			 while (ReadBuffer[1] != 0) {
				 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 218, ReadBuffer, 1);
				 ReadBuffer[1] = (ReadBuffer[0] & 0x19);
				 //ReadBuffer[1] = (ReadBuffer[0] & 0x15);
			 }

			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 218, ReadBuffer, 1);
			                          xil_printf("5338Reg[218] = %d\r\n", ReadBuffer[0]);

			 //Copy FCAL values to active registers

			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 235, ReadBuffer, 1);
			 WriteBuffer[1] = ReadBuffer[0];
			 WriteBuffer[0] = 45;
			 Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);

			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 236, ReadBuffer, 1);
			 WriteBuffer[1] = ReadBuffer[0];
			 WriteBuffer[0] = 46;
			 Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
			 //!!
			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 237, ReadBuffer, 1);
			 //WriteBuffer[1] = (0b00010100 | (ReadBuffer[0] & 0b00000011));
			 //WriteBuffer[0] = 47;
			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 237, ReadBuffer, 1);
			 WriteBuffer[0] = (ReadBuffer[0] & 0b00000011);
			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 47, ReadBuffer, 1);
			 WriteBuffer[2] = (ReadBuffer[0] & 0xFC);
			 WriteBuffer[1] = (WriteBuffer[0] | WriteBuffer[2]);
			 WriteBuffer[0] = 47;
			 Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
/*
			 //Set PLL to use FCAL values Set FCAL_OVRD_EN = 1; reg49[7]
			 Status = Orbbec_iic_recv_data(IIC_SI5338_ADDRESS, 49, ReadBuffer, 1);
			 WriteBuffer[0] = 49;
			 WriteBuffer[1] = (ReadBuffer[0] | 0x80);
			 Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);
*/
			 usleep(25 * 1000);

			 WriteBuffer[0] = 230;
			 WriteBuffer[1] = 0x00;
			 Status = Orbbec_iic_send_data(IIC_SI5338_ADDRESS, WriteBuffer, 2);


    return Status;
}

Thanks a lot in advance,

Yuming Lou
 

In the system "SI5332A-D-GM1"  "SI5347D-D-GM" "SI5394M-A-GM" timing devices. I want to know what is the maximum reprogramming of the NVM for all three devices.

checked and got confused .....

for SI5347D  " 3.10 In-Circuit Programming" -> The NVM is two time writable

https://www.silabs.com/documents/public/data-sheets/Si5347-46-D-DataSheet.pdf

for SI5332A  "2. Frequency Plan NVM Program" ->  “Re-configure” the NVM as many times as possible

https://www.silabs.com/documents/public/application-notes/an1109-programming-options-si5332.pdf

why it is so different and am I correct ?

Need your help to find the right answers.

Tnx

Hanan

I have to get a couple of synchronized signals above 150 MHz out Si5351 clocks.

Initially I disconsidered adding a  Si5351C clock with its CLKIN Input.

I thought on coupling a Si5351a Xb, crystal output on another device Xa crystal input. But somehow the crystal clock signal went off as soon Xb connected with Xa.

First Si5351a was running programmed at a given frequency. The second one was simply running at registers default status power up.

Any idea about how to synchronize and couple a couple of Si5351 crystal signals?

Thank you in advance!

I'm trying to get confirmation of what the outputs of the Si53340 are doing at power-up.  I'd imagine that they're in a HiZ state, but I can't find any references.

My application is using the Si53340 to distribute LVDS signals to several frontend components. The front end components run at 2.5V.  While I realize the Si53340 can run on 2.5V, for ease of power distribution (related to placement and layout) it would be more convenient to use 3.3V on them. Since I'm using LVDS, the downstream components shouldn't care if the buffers are powered with 3.3V or 2.5V. However, there is come concern that on power up there may be some transients on the Si53340 outputs. Which is why I'd like to get confirmation of what the outputs are doing at power up. Thanks!

Anyone have an idea of what I should expect in the way of non-harmonic spurious outputs? How about crosstalk between output channels? Noise expressed as dB/Hz at different frequencies?

Joe

I am using ClockBuilder Pro 2.45 to export a register c header file for a SI5332B-D-GM1. Unfortunately the header file uses identifiers with a - which is not valid c.
Examples:
#ifndef SI5332-GM1_REVD_REG_CONFIG_HEADER
si5332-gm1_revd_register_t const si5332-gm1_revd_registers[SI5332-GM1_REVD_REG_CONFIG_NUM_REGS]

As far as I am aware I cannot configure these names, but at the very least it is a poor default. Obviously I can manually edit and fix the file, but experience tells that manually editing an automatically generated file is a bad idea.

I tried the same with a random another device (SI5344) and the export uses underscores as it should.

Hi,

I'm working through programming the Si5332H-D-GM1 with clockbuilder pro software and field porogrammer. I am finding I need multiple programming attempts to get the NVM to program:

First attempt: Fail

Second attempt: Says it's programmed but it didn't

Third attempt: Success.

Is this a known issue?

Hello, 

I am trying to use the EFR32FG14 in an application that requires very fast startup time (<1ms). If I understand the datasheet correctly, the device should be able to go from power down to receiver ready in <1mS. However, all measurements I have been making are about 15 mS. 

For now, I am trying to just do a simple power-up, initialize the radio, and enter receiver mode. I suspect that the device is doing more than that. If someone could point me to a simple script that will allow the part to boot up an enter receive mode as fast as possible, I would greatly appreciate it.