Hi,

I have designed a PCB to test clock recovery and distribution with a SI5394K Jitter cleaner in order to reduce the BOM on the board. It seems that SI5394/95 with internal reference are non stocked and the purchasing delay is very long (12 weeks...). I have 2 questions :

1 - What is the plan for the SI5394/95 with internal reference ? Should we considerate that SI5394/95 with external XTAL is a better long term solution ?

2 - If I assemble on my existing PCB an available SI5494 A/B/C/D chip without external XTAL for quick tests, will it work ?

Thanks for your colaboration

Hi, after flashing the evb with my settings the outputs stops working/disabled what is the cause behind this all inputs are connected except the XA/XB as i read in the si5383A evb that it was optional please suggest quick solution to bring the evb in working mode so i can continue my work that is stayed

I am using an Si5340 and need the lowest phase noise I can get. Since SC cut crystals tend to have lower phase noise than AT cut crystals I would like to know if I can use one on the XA,XB pins of the Si5340.

Neither the spec sheet nor reference manual mention cut at all.

Thanks,

John S.

Hello guys.

I'm using Si5351A for transmitting on 14 MHz frequency. My chip has 3 clocks (CLK0, CLK1 and CLK2).

I would kindly ask you if it is possible to transmit (generate clock signal) at same time on two different frequency, e.g. 14097100 and 14097200 Hz.

In particular, if that is possible using same antenna (same wire connected to CLK0 and CLK1 for example).

Thank you so much for your appreciated help.

Roberto.

I'm looking into use of the Si5341 clock generator and setting my my design for use of the zero delay mode. In reading through the datasheet I noticed that in zero delay mode section the crystal input is not included in the block diagram (attached). There are other block diagrams where the crystal input is present but given the discrepancy I wanted to make sure there weren't any limitations between using the zero delay mode with either the crystal input or one of the other clock inputs.

Thanks.

Just found this through Clock Builder Pro (below) but I don't see reference to this anywhere else...

How to switch the reference clock from XAXB to one of IN0~4 quickly as flash?

When initializing the Si5394, I want to run from XAXB reference first, then I will change the reference clock to IN1 at a set time. How can l realize it without pausing or shutting down the OUTPUT? because there are services running depending on the si5392 output clock.

I want to use an external clock of 50MHz, and then configure si5394 to output out1 25MHz.I configure the registers as follows.I set up a lot of registers, such as xaxb_ EXTCLK_ EN、PXAXB、N0_ Num and so on. But it doesn't work. Are there any special steps or registers that I need to set

 

 

Hi,

the datasheet for the 5340 Rev D shows on page 20 a minimum input clock frequency of 8 kHz for all methods (AC-coupled single ended and differential, DC-coupled pulsed CMOS). However, I can't get ClockBuilder Pro to go below 10 MHz. Is that a mistake on the datasheet or can it be programmed manually to go below 10 MHz?

Also on the datasheet on page 1 it says "Locks to gapped clock inputs", but elsewhere I see that I need to supply a pretty clean clock (as far as phase noise/jitter), and since a gapped clock is basically has lots of non-random jitter I don't understand  how it works for non-random jitter but it fails for random jitter. Is this also a mistake on the datasheet or I should be able to lock to a gapped clock?

Finally, while doing some tests I generated some register settings from ClockBuilder Pro that work but don't match what the reference manual (Rev 1.3) says. For example, the "Clock Output Format 0" register has address 0x0109 in the reference manual, but 0x0113 in the code generated from ClockBuilder Pro. Is this due to the fact that the output numbers in the manual are for the 5341 and they don't match the 5340? The figures like fig 1.1 in the manual seem to suggest that the 5340 retains the first 4 outputs, but is it the case that really output N on the 5340 is output (N+2) on the 5341?

Thank you

HI, guys,

  I meet a strange question about SI5338A .

  I layouted my test demo, I  used 25MHz input reference to IN3, VDD & VDDO are both 1.8V.  The device was in normal I2C write & read communication. 

  In my test, I programmed the device to output 100MHz LVDS clock  in both 4 channels, the register configurations were made by the the CBPro Tools. 

  During the  initialization process, I need to configure the PLL lock status, to see if the PLL is locked.  

  But I found that the code was stucked in the while loop as follows

//make sure the device locked by checking PLL_LOL and SYS_CAL
reg = I2C_ByteRead(218) & LOCK_MASK;
while(reg != 0){
reg = I2C_ByteRead(218) & LOCK_MASK;
}

I check the value of register 218, it was 0x09, which means SYS_CAL was assert 1 all the time.   

I also checked other register values wrote to the device before this loop and they are OK. 

So, I tried to ignore this and continued to complete the rest registers, it was no use. No outputs turned on ch0~ch3.

Is there anybody who have even been in the same situation ?

Thanks.

Hallo dear customer care representative.

I'm an hobbyist using Si5351A in a system controlled by ATmega328P-AU microcontroller.

The purpose is to transmit WSPR (Weak Signal Propagation Reporter, wsprnet.org) messages.

The WSPR typical message is made by callsign, locator and dBm values.

For example, one of these messages mey be IZ7VHF JN80 10. It means IZ7VHF is my amateur radio callsign, JN80 is my geographical position expressed with Maidenhead Locator codification, and 10 is my signal strenght.

Now, if I try to transmit some other messages, like DD2DDD  DD22 17, the Si5351A transmit fine, but decoding software is unable to decode it.

Probably there may be a very "microscopic" difference in the signal generated.

As you can see in the attached file, there are 3 signals on the waterfall: the one with "OK" below has been correctly decoded. The other two with "NO" mark has been not decoded.

The voltage on VCC input is 4.205V, so like specifications, it is ok. No any andvantages if I put 3.3V.

In your opinion, there may be something wrong in the configuration?

Thank you for your help. I appreciate.

Roberto.

 

Hi, We are using  SI53301-B-GM, Si53302-B-GM and SI53307-B-GM clock buffers in our design for clocking solution, and need the design review support. 

 

Attaching the schematics. 

 

We are considering using Si53344 in one of our designs but are concerned about the Propagation Delay of 650 - 1050 ns that is shown in the datasheet.  This value seemingly wouldn't support the 1250 MHz maximum frequency so we were wondering if this is a typographical error in the datasheet - that perhaps the Propagation Delay values shown are in picoseconds rather than nanoseconds.  Can you confirm the correct propagation times for these parts?
 

I am using ClockBuilder Pro 2.45 to export a register c header file for a SI5332B-D-GM1. Unfortunately the header file uses identifiers with a - which is not valid c.
Examples:
#ifndef SI5332-GM1_REVD_REG_CONFIG_HEADER
si5332-gm1_revd_register_t const si5332-gm1_revd_registers[SI5332-GM1_REVD_REG_CONFIG_NUM_REGS]

As far as I am aware I cannot configure these names, but at the very least it is a poor default. Obviously I can manually edit and fix the file, but experience tells that manually editing an automatically generated file is a bad idea.

I tried the same with a random another device (SI5344) and the export uses underscores as it should.

Here i have a question  of the date code & seal date issue.

is it possible of the product date code is 1625 & the Seal date is 07-Jan-19?

Thanks.

I can get close :-)

Running a 25Mhz crystal

using a Multisynth divider of 1317 and an r_div of 4 I can get to 132.8779 (a delta of 0.0423)

using a Multisynth divider of 1318 and an r_div of 4 I can get to 132.7771 (a delta of 0.0585)

Can anyone guide me to getting right on my target?

Thank you,