Hello,

I'm trying to configure an  Si5340 device using ClockBuilder Pro. I read in the reference manual that in order  for changes to N dividers to take  effect, one must  write 1 to an N_UPDATE register.

However, I noticed that in the register configuration generated by ClockBuilder Pro these update registers have 0x00 written to them.

does this mean the update happens in some other way or is it my responsibility to write 1 to these registers.

( I don't have the device yet so I can't test my firmware to see what works) 

thanks

Hello

I'm using  Si5341A-D09088-GM in my project. Please let me know the current requirement of 3.3V (VDDA+VDDO9) and 1.8V (VDD+VDDO) power rail.

Regards

Nidhi P Shetty

Hello,

I'm trying to configure an  Si5340 device using ClockBuilder Pro. I read in the reference manual that in order  for changes to N dividers to take  effect, one must  write 1 to an N_UPDATE register.

However, I noticed that in the register configuration generated by ClockBuilder Pro these update registers have 0x00 written to them.

does this mean the update happens in some other way or is it my responsibility to write 1 to these registers.

( I don't have the device yet so I can't test my firmware to see what works) 

thanks

Hello, please tell me what is the input resistance of this chip? I think it’s 10k, but I’m not sure, since it’s written in the datasheet that it’s for 1in and 3in inputs, but for 3in input, nothing is said ... I have a Si5330L-B00230-GM chip

Hello,

i have a custom board with an un-programmed Si5332 soldered to it.

Writing the design to the device with CB V2.29 is working without problems via I2C and CBpro Field Programmer.

But programming the device is refused with the error message: Not enough NVM space available to burn plan.

Checking the NVM state gives: 137 frames used, 0 bytes available to burn, see attachement.

Are there special considerations I have to take to perform a NVM program?

Thanks

Detlef Wolf

 

Hi, 

What is the internal impedance of this oscillator? I need this impedance to model the oscillator in the HyperLynx. I have looked at the datasheet but unsuccessful. 

Thank you.

Regards,

Paul Brar

 

 

Hello, please tell me what is the input resistance of this chip? I think it’s 10k, but I’m not sure, since it’s written in the datasheet that it’s for 1in and 3in inputs, but for 3in input, nothing is said ... I have a Si5330L-B00230-GM chip

How do you configure the SI5335D for differential outputs using Clock Builder Pro?

Hi,

We are using Si5324 to clean jitter froma clock comming from an FPGA. Our input CLK is 74.25Mhz and we expect the same frequency at the output. We are using a 3rd overtone cristal (ABM8-116-114.285MHZ-T). After programing the device we see at the output 19.44Mhz, that seems like the default configuration.

The clk input is LVDS and so is the output. We have set the device in free run and still we see the same freq. This is the register map qe have loaded

#HEADER
# Date: Thursday, February 7, 2019 11:32 AM
# File Version: 3
# Software Name: Precision Clock EVB Software
# Software Version: 5.1
# Software Date: July 23, 2014
# Part number: Si5324
#END_HEADER
#PROFILE
# Name: Si5324
#INPUT
# Name: CKIN
# Channel: 1
# Frequency (MHz): 74.240000
# N3: 4529
# Maximum (MHz): 85.909090
# Minimum (MHz): 73.484848
#END_INPUT
#INPUT
# Name: CKIN
# Channel: 2
# Frequency (MHz): 114.269604
# N3: 6971
# CKIN2 to CKIN1 Ratio: 6971 / 4529
# Maximum (MHz): 132.230574
# Minimum (MHz): 113.107281
#END_INPUT
#PLL
# Name: PLL
# Frequency (MHz): 4899.840000
# XA-XB Frequency (MHz): 114.269605
# f3 (MHz): 0.016392
# N1_HS: 11
# N2_HS: 11
# N2_LS: 27174
# Phase Offset Resolution (ns): 2.24497
# BWSEL_REG Option: Frequency (Hz)
#  4:    5
#  3:   10
#  2:   20
#  1:   42
#END_PLL
#OUTPUT
# Name: CKOUT
# Channel: 1
# Frequency (MHz): 74.240000
# NC1_LS: 6
# CKOUT1 to CKIN1 Ratio: 1 / 1
# Maximum (MHz): 85.909090
# Minimum (MHz): 73.484848
#END_OUTPUT
#CONTROL_FIELD
# Register-based Controls
#        FREE_RUN_EN: 0x1
#    CKOUT_ALWAYS_ON: 0x0
#         BYPASS_REG: 0x0
#          CK_PRIOR2: 0x1
#          CK_PRIOR1: 0x0
#          CKSEL_REG: 0x0
#              DHOLD: 0x0
#            SQ_ICAL: 0x1
#          BWSEL_REG: 0x4
#        AUTOSEL_REG: 0x2
#           HIST_DEL: 0x12
#              ICMOS: 0x3
#              SLEEP: 0x0
#         SFOUT2_REG: 0x1
#         SFOUT1_REG: 0x7
#          FOSREFSEL: 0x2
#             HLOG_2: 0x0
#             HLOG_1: 0x0
#           HIST_AVG: 0x18
#          DSBL2_REG: 0x1
#          DSBL1_REG: 0x0
#             PD_CK2: 0x0
#             PD_CK1: 0x0
#         FLAT_VALID: 0x1
#             FOS_EN: 0x0
#            FOS_THR: 0x1
#            VALTIME: 0x3
#              LOCKT: 0x1
#        CK2_BAD_PIN: 0x1
#        CK1_BAD_PIN: 0x1
#            LOL_PIN: 0x1
#            INT_PIN: 0x0
#         INCDEC_PIN: 0x1
#       CK1_ACTV_PIN: 0x1
#          CKSEL_PIN: 0x1
#        CK_ACTV_POL: 0x1
#         CK_BAD_POL: 0x1
#            LOL_POL: 0x1
#            INT_POL: 0x1
#           LOS2_MSK: 0x1
#           LOS1_MSK: 0x1
#           LOSX_MSK: 0x1
#           FOS2_MSK: 0x1
#           FOS1_MSK: 0x1
#            LOL_MSK: 0x1
#              N1_HS: 0x7
#             NC1_LS: 0x5
#             NC2_LS: 0x5
#              N2_LS: 0x6A25
#              N2_HS: 0x7
#                N31: 0x11B0
#                N32: 0x1B3A
#         CLKIN2RATE: 0x0
#         CLKIN1RATE: 0x0
#           FASTLOCK: 0x1
#            LOS1_EN: 0x3
#            LOS2_EN: 0x3
#            FOS1_EN: 0x1
#            FOS2_EN: 0x1
#   INDEPENDENTSKEW1: 0x0
#   INDEPENDENTSKEW2: 0x0
#END_CONTROL_FIELD
#REGISTER_MAP
  0, 54h
  1, E4h
  2, 42h
  3, 15h
  4, 92h
  5, EDh
  6, 0Fh
  7, 2Ah
  8, 00h
  9, C0h
 10, 08h
 11, 40h
 19, 39h
 20, 3Eh
 21, FFh
 22, DFh
 23, 1Fh
 24, 3Fh
 25, E0h
 31, 00h
 32, 00h
 33, 05h
 34, 00h
 35, 00h
 36, 05h
 40, E0h
 41, 6Ah
 42, 25h
 43, 00h
 44, 11h
 45, B0h
 46, 00h
 47, 1Bh
 48, 3Ah
 55, 00h
131, 1Fh
132, 02h
137, 01h
138, 0Fh
139, FFh
142, 00h
143, 00h
136, 40h
#END_REGISTER_MAP
#END_PROFILE

 

Do you have any clue on what might be happening?

 

Thanks

Does Si5351 support repeated start on I2C?

i'm wondering dose silab provide any api for us to configure the si5345 using python or powershell etc..?

 

Hi, it looks I have 2 serious problems:

1. It seems that my Si5351-A-B devices can not lock PLL at frequencies over about 820 MHz (tried 2 pcs). Turning off all of the outputs and adding more decoupling capacitors close to the device has no effect.
2. As well, I found out, the VCO can be tuned down all the way to 185 MHz where it seems to have tuning limit. Setting multiplier value to obtain lower frequency of PLL than 185 MHz results in PLL staying at the tuning limit with glitches. To get to the problem - LOL_A and LOL_B do not get set. According to AN-619, they should be set when (citation) "... loss of lock will occur if the frequency of the reference clock forces the PLL to operate outside of its lock range ...". Clearly, this is situation where the PLL is driven out of lock (more than 3 times lower than specified in datasheet!), but no indication whatsoever of this happening.

Are these bugs known and existing in all of Si5351 devices or is it an out-of-spec (and damaged when it comes to point 2) batch?

Originally asked on Twitter: https://twitter.com/polasek_petr/status/964611137185697792

I n clock builder pro , in step 3 we define input signal (clk2 or xtal) which must be configured as differential or LVCMOS. I need LVCMOS option (default is differential). I don't possibility to change this option from differential to LVCMOS.

I'm working with the Si5345-EB REV 2.1, which I'm able to configure using the ClockBuilder Pro software. Once the design is transferred to the EVB, everything works as expected.

Next step for me is to achieve the same programming using a c bare-metal program installed in an external microcontroller. To this end, I first generate the configuration file with the ClockBuilder to be added to the C program, and the spi bus of the microcontroller (4-Wire at 1.8 V, not 3.3 V!) is connected to the spi interface of the evaluation board (J36, with the jumpers removed). 

I have read and understood how the spi programming sequence is (an926-reading-writing-registers-spi-i2c.pdf), and, indeed, I'm able to write and read the whole set of registers provided in the configuration file (I write them all and then read them again to check if they were correctly written; apparently, they are). However, when I run this program, that writes the preamble, configuration registers and post-amble, the clocks never start. 

There is a single exception: if I program the clock with the clockbuilder, then connect my spi and finally reset the clock, then the clock starts correctly after running my code. Basically, if the chipselect of the spi bus is kept high while reseting, then my software is able to start the clock properly. I assume that this is due to some configuration that the ClockBuilder is doing and my software isn't, and remains in memory even after reseting the clock if the chipselect is kept high. Any suggestion about which could be this configuration? Am I missing anything else?

Some additional information: as commented, I'm using the default file provided by ClockBuilder Pro. I've also tried adding the additional registers that clockBuilder is programming but not adding in the configuration file (and that can be obtained via the clockBuilder EVB GUI). The jumper JP4 is kept in the evaluation board (I2C_SEL = 0) and IO_VDD_SEL = 0 via 0x0943 (1.8 V). There is no reference, so the clock should start in free run mode.

 

This is a similar question to https://www.silabs.com/community/timing/forum.topic.html/si5345_input_to_outp-DPc7 :

For an eg. Si5341 : if I have an input 48MHz xtal with 20 ppm, and I'm generating a 100MHz clock, is the 20ppm of the crystal passed to the output?

The 20ppm means that the crystal is not drifting, just statically not quite at the marked frequency by +/- 20ppm, right?  (Assuming a fixed temperature and voltage). 

 

Thanks,

-m