Hello,

I am trying using collect both single ended and differential measurements using Version 4.0 of the PCIe Clock Jitter Tool.  The differential waveform seems to process correctly, but the single ended waveforms do not. I get "Error processing wave data" error.   These same waveformes, both differential and single ended, will process without error in Version 3.0 of the PCIe Clock Jitter Tool.

Here is some info on my setup.

Tektronix DSA 73304D
Ch1: REFCLK+
Ch3: REFCLK-
Scale set to 50mV which is the lowest possible until cropping the waveform
Termination 50 OHM
DC Coupling
Bandwidth: 20GHz
Digital Filters (DSP) Enabled
Force Constant Sample Rate Enabled
Constant Sample Rate Enable
Sample Rate 50.0GS/s
Scale 200us

Math1: Ch1-Ch3
Scale set to 100mV which is the lowest possible until cropping the waveform

All three waveforms (Ch1, Ch3, and Math1) are saved as .wfm files.

In Version 4.0 [6/17/2019] of the PCIe Clock Jitter Tool I use the following steps:
For Differential Measurements:
1. Create New Compliance Project
2. Data Category: Time Domain
3. File Type Differential
4. Differential Voltage Threshold set to Manual threshold set to 0 V
5. Select Math1 Waveform
6. After processing, select only GEN3 Common Clock

For Single Ended Measurements:
1. Create New Compliance Project
2. Data Category: Time Domain
3. File Type Single Ended
4. Differential Voltage Threshold set to Manual threshold set to 0 V
5. Select Ch1 and Ch2 Waveforms
6. After pressing the Next button, I get an Erro processing wave data message.

As for debuging, I have tried changing the Differential Voltage Threshold Manual setting and setting it to Auto-threshold.  I have also tried swaping the two waveform files.  I still can not get the waveforms to process using the Ver 4 software.

Hello!
i have two SI5338P. For example D1 and D2.
D1 is programmed and work fine. But  D1.clkout3 is used for D2.clkIN
i use differential LVDS2v5 out3  100MHz to -> dif in1/in2

 

.                           |---- D1 ----|                  |---- D2 ----|
source clk_p->--|--[0.1uF]--|1          9|------|--[0.1uF]--|1          9| ...
.           [100OHm]        |            |   [100OHm]       |            |
source clk_n->--|--[0.1uF]--|2         10|------|--[0.1uF]--|2         10| ...
.                           |____________|                  |____________|

D1 reg247 - 0x08
D2 reg247 - 0x1C (PLL_LOL=1, LOS_FDBK=1, LOS_CLKIN=1)
FDBK not used. reg6 - 0x08

Both PLL have termination and 0.1uF, according to recommendations Figure 3 in Datasheet.
When D2 is connected - oscilloscope show ~100mV Vpp
if D2 is disconnect (remove r100 and 0.1uF), output D1 is great ~1.3V Vpp

What is the possible problem?

ps: in https://www.silabs.com/documents/public/application-notes/AN408.pdf 
3.4. LVDS Outputs says:
The LVDS driver may be dc-coupled or ac-coupled to the receiver in 3.3 V or 2.5 V output mode
Can i use DC-Coupled if LVDS source is D1?

Thanks

We have purchased the SI5338 Field Programming kit and need to know how to program with a hex file. Does anyone know how to do this?

I want to try the si5340 so i purchased one and soldered it to a qfn adapter. I connected the pins:

VDD pins to 1.8v

VDDA pins to 3.3v

VDDO pins to 3.3v

VDDS to 3.3v

I2C_SEL to GND

IN_SEL0 and IN_SEL1 to 3.3v

27 mhz xtal to XA, XB pins

I cant communicate the IC whatever I do. When I look at the RSTb pin with oscilloscope I see the pattern in the photo below.

I think the IC finds something wrong and restarts itself but i cant find what's wrong. Any help would be appreciated.

Hello,

My goal is to create synchronized Low jitter clocks on 2 (or more) different cards (clocks inside each card and among all cards), using splitted 1PPS signal to each card, from external source.

I also need to use the same 1PPS to sample it later using one of these clocks (using FPGA etc.).

I'm looking for the best way to accomplish it.

I saw the si5383-84, which seems to be capable of synchronizing with 1PPS.

The question is:

Can I get a constant delay (on all different si5383-84 devices located on all the cards) between the input (1PPS) and the output clocks?

In other words, is there any "zero delay" mechanism?

(As for the 1PPS, the tDELAY_1PPS parameter from the datasheet, varies between -10 and 10 ns, meaning maximum varience of 20ns among cards, is it correct?)

Thanks!

Max

I am using Si5394A RevA EVB and ClockBuilder Pro v2.35

Trying to set Reference to XO 100MHz but the entry window says "Frequency Range 24.97MHz to 54.06MHz"

I know that the part has divider in XO path that can be set to 1/2/4/8 and manual says:

" For best jitter performance, use a XAXB frequency above 40 MHz. Also, for XAXB frequencies higher than 125 MHz, the PXAXB con-trol must be used to divide the input frequency down below 125 MHz"

" A PREF divider is availa-ble to accommodate external clock frequencies higher than 54 MHz "

Is this a bug, a feature or a trick?

Leo

 

Hi,

I have an application for the si5332B-GM1 requiring 19.2MHz generated from 30MHz, or a division of 1-9/16 or 1.5625.  I believe in order to do this with 0 PPM error a modulus 16 fractional-N divider, or any 2^N modulus > 16 like 32 or 64 would be needed.

I suspect the chip can do this, and I will be ordering an eval PCB to prototype and confirm.  Are there any users familiar with this part that can confirm what modulus' (moduli?) are available for fractional-N?  I did not find these listed in the datasheet.

Hello all,

My goal is to generate 6 synchronous clocks using the Si5351. The clocks have different frequencies. But the phase offset between all the clocks has to be fixed.

It seems to work. However, I am observing an intermittent problem where the phase offsets between clock outputs seems to be random. See below:

Observed:

Expected:

Using the following steps, I am able to reproduce the issue:

i2c_write:  [bb-82]   # Enable fanout of CLKIN

i2c_write:  [10-6c]   # Powerup clk0, integer mode, MS0
i2c_write:  [12-6c]   # Powerup clk2, integer mode, MS2
i2c_write:  [14-6c]   # Powerup clk4, integer mode, MS4
i2c_write:  [11-6c]   # Powerup clk1, integer mode, MS1
i2c_write:  [13-6c]   # Powerup clk3, integer mode, MS3
i2c_write:  [15-6c]   # Powerup clk5, integer mode, MS5

i2c_write:  [b1-80]   # Reset PLLB
i2c_read:   [b1]      # Wait until the reset bit is cleared

i2c_write:  [03-00]   # Enable all clock outputs

  # All clocks should be enabled and in sync now
  # Disable the clocks (not shown for brevity)
  # Repeat (enable the clocks again)

In 1 of 20..100 runs the clocks are not in sync.

How can I ensure that the clocks are always in sync?

Thanks

 

As title, the antivirus Avira found that there is virus included in the downloaded ClockBuilder Pro, Version 2.28.1 [2018-09-24].

We use Si53321-B-GQ in one of our product. This part is obsolete and we cannot find a drop in replacement part. Can you recommend one?

Can Pericomp PI6C4911510-05FAIE a replacement part?

Thanks,

Lik

Hello sir/madam,

There is a requirement of two clock output in our design so we are planning to go with SI5350C-B 10MSOP IC for our design. We are finding difficulties in how to configuring the output clock frequency. there is no detailed information about how to configure the output clock in the datasheet e.g. 34MHz for CLK0 and CLK1.  Kindly guide us and please let us know if you need any further information.

Thank you,

regards,

Abhishek

I am using si5340 to generate two signals at 900Mhz and 910Mhz from two different output of the board. However, I get an error says that this frequency cannot be synthesized due to Fvco of 13.65 GHz, set by the highest freq output 910Mhz in your design. For the configuration, I use one of the input port as a reference clock signal at 10 Mhz.  Is there any way to exceed this limitation?

Manufacturer Description	MPN
SILICON LABORATORIES	SI53156-A01AGMR

Silicon lab’s Tape and Reel guide contains 6 options for QFN-32, 5x5 package.

Can you please let us know which one is suitable for above part number.

Refer attached figure.

Hello,

I am trying to program a SI5340B-D-GM from my Xilinx SoC on a custom board.

I created the register map using ClockBuilderPro 2.35 (exported as registers.h)

- I2C is initialized to 100kHz

- I created an utility si5340_write function with a register_address (u16) and data (u8) that works in this way:

   - page_byte and register_byte are extracted using the shift operator as in reference manual example

   - I2C write operations are accomplished using Xilinx XIicPs_MasterSendPolled

   - I send the page _byte to the slave device

   - I send the reg_byte to the slave device

   - I send the data (single byte) to the slave device

   - write status returned by I2C driver is always 0 (successfull)

then I use this function to perform the following algorithm:

- I call si5340_write in sequence for the first 6 (index 0->5) entries of si5340_revd_registers array in registers.h (preamble)

- I wait 300 milliseconds (using usleep(300*1000))

- I call si5340_write in sequence starting from index 6 to SI5340_REVD_REG_CONFIG_NUM_REGS - 1 for the remaining registers of si5340_revd_registers array in registers.h (postamble is included)

 

Unfortunately this is not enough for the si5340 to produce anything on the outputs pins.

Reading register 0x000C gives this output: 0xC9

this should mean SYSINCAL and LOL status bits true, am I right?

 

My hardware is set up as follows:

- 48 MHz crystal quartz  on XA/XB pins (IN_SEL0/1 pins tied high) as input for best jitter performances (load capacitance of 4pF and typical ESR less than 18 ohms (30 ohms max.))

- Outputs DC coupled with 100 ohms differential termination impedance and impedance controlled traces.

- RSTb pin tied high with a pull up resistor

- Powers: VDD at 1V8, VDDA at 3V3,  VDDO0/1 at 1V8 and VDDO2/3 at 3V3

- Other input source pins (IN0/1/2) and Feedback (FB_IN) are left floating

 

I've checked with the oscilloscope the crystal pads and they still doesn't oscillate (that's why I think that the output still stay low and the PLL is unable to lock.....but why seems that the chip is not able to drive it?).

Anyone is able to help me with this problem?

Thank you in advance

I am trying to initialize the Si5346 using the register map generated from the ClockBuilder tool. However, I had a question regarding the writing of pre and postamble sequence. In the Reference Manual, in 3.1.1.1, it states to "write the preamble by updating the following control bits using the Read/Modify/Write Sequences" and it gives a table with the address and the value. However, usually with Read/Mod/Write, there is a data mask that defines which bits should be changed during the read/mod/write operation, but I cannot actually tell which bits should be modified. Even when looking at the details of these pre/postamble registers, the entire 7:0 bits are R/W so I can't deduce a write mask.... Or is the read operation, just part of the "sequence" and I just end up writing the value specified regardless?