my code is at https://github.com/gomer-grondin/si5351a.git
I'm using an Adafruit si5351A with 25Mhz crystal.
here is my plan for 3.1Mhz :
Frequency = 3.200000 Mhz, Scale = 100Khz INTEGER
Frequency = 3.100000 Mhz, Scale = 100Khz FRACTIONAL INTEGER solution overwrote current solution
Frequency = 3.100000 Mhz, Scale = 100Khz INTEGER
my oscilloscope reads 2.323 Mhz when I implement this plan. I believe that the plan is correct, can you assist?
here is the plan for fractional mode 3.1Mhz
FRACTIONAL solution overwrote current solution
Frequency = 3.100000 Mhz, Scale = 100Khz FRACTIONAL
which my scope verifies as 3.1Mhz. my issue is that I have not found a way to predict which frequencies have this problem.
there are 31 other frequencies that I've identified that have the same issue:
in Mhz .. 2.7, 2.9, 3.1, 3.3, 3.7, 3.9, 4.1, 4.3, 4.8, 5.2, 5.4, 5.6, 5.8, 6.2, 6.4, 6.6, 6.8, 7.2, 7.4, 7.6, 7.8, 8.2, 8.4, 8.6, 8.8, 13.5, 14.5, 15.5, 16.5, 18.5, 19.5, 20.5
I've manually checked from 100khz to 20.5Mhz incremented by 100khz, so the error rate is 31 out of 250 total frequencies or 12.4%
of the 250 frequencies in the testing set, 117 have no valid integer mode solution. (i.e. 700khz, 4.7Mhz, 10.2Mhz, etc)
of the 133 that have an valid integer solution. 31 problem frequencies represents 23.3%
I have not discovered a programmatic way to predict which frequencies have this problem. Should I revert to fractional mode only?
or, have I blundered the code somehow?
thanks for your attention.
Can anybody please help me by providing the temperature vs current characteristics of SI5328C-C-GM IC.
Thanks & Regards,
Can i use the Si5383-D-EVB board to program another customized SI5383 pcb instead of using the CBPRoG dongle?
If so, where can I find the procedures ?
I am using EFR32MG12 board,
I have been working on a part where I have to hold GPIOpin high for 62 milli seconds, and pull it back to low state after it without using delay function(or only delay function is the way), is there any API or setup for it
Any leads will be helpful
pls send me the transient from input switching and jitter measurement from DCO adjustment, and the output transient between input enter and exit holdover, the output is 122.88M for wireless application.
Can you help to put the SW and application note on how to generate the configure file for input switching? （ pls put a sample code for switching between 10M, 13M and 10.74M at IN2 and IN3 separately)
Very simply, I just want the project file of 'ClockBuilder Pro' to set Si5341B-B05071-GM in ZCU102.
If not, how can I set Si5338C for ZynqMP PS GTR REF clock(100MHz, PCe) and PCIe slot clock(100MHz).
My hardware schematic is below,
And I set as below.
Is it correct?
My objective is to create 10 clocks that are synchronous, however, 8 of the clocks will have spread spectrum (SS) and 2 of the clocks will have no SS. To do this, I would like to use the 25Mhz Reference Clock output of the si52208 to drive the XIN/CLKIN of a si52202? Questions:
1) Can I use the 25MHz Reference Clock of the si52208 to drive the XIN/CLKIN of a si552202 to get 10 synchronous clocks?
2) What is the ppm (tolerance and stability) of the 25Mhz reference clock on the Si52208? Is it the same as the Crystal provided on the XIN/XOUT pins of the Si55208 or is there some additional ppm I need to add to the 25MHz reference clock?
3) Pls note that I will eventually turn on SS in the si55208 but not in the si52202. Do you see any issues with this.
Thank you for your time
It looks like the Si5336x family is very similar to the Si5330x parts but I'm having a hard time finding documentation supporting some of the Si5336x functionality or lack thereof.
Can the Si5336x (specifically looking at the Si53362) be configured to drive at at a lower output voltage like the Si5330x parts? Specifically, can it be configured to drive at 1.2V? The Si5330x datasheet indicates that 1.2V drives can be achived with a simple voltage divider (see image taken from Si5330x datasheet):
I'd like to use a similar approach with the Si5336x but it's not explicitly called out as a possibility in it's datasheet. Given that the chips have different drive strengths I'd not sure if this is something that would work for both.
Can Vdd and Vddo be run at different levels? Like the Si5330x there are separate input pins for Vdd and Vddo but the datasheet does not indicate that they are independent supplies. In fact the datasheet only has electrical specifications for Vdd and nothing for Vddo. Should this be interpreted implicitly as applying to both Vdd and Vddo?
I wanna use Si53302's LVCMOS outputs to drive about 20 PLLs, in Table 3.10 of the datasheet there has a parameter: Output to Output Skew, does this parameter apply to Qx and Qxb pin or their skew is better than it?
I have a question about Si5386. As described in datasheet once locked, the DSPLL generates output clocks that are frequency and phase locked to their selected input clocks. Do I correct understand if I will feed clock signal with same frequency and phase to same clock inputs of two different Si5386 I can get stable and repeatable phase difference between outputs of both the Si5386's?
I have one question regarding the programming of the Si5386A.
Is it possible to program the Si5386A using only writes on the SPI interface? Without read operations? Or are they necessary. Due to a design mistake my microcontroller does not support 3-wire SPI.
Is it possible to use a 4 wire SPI interface without the read line for programming?
What is the full device programming procedure?
Yes, in some cases, the full procedure may not be needed in all cases, but the following is the general procedure recommended for most cases. These writes are added automatically by CBPro software when using a Silicon Labs evaluation board and also when exporting register and setting files for use in the end system.
So I understand that no read operations are needed.