I'd like to generate an LVDS clock output from a 1.2Vpp LVCMOS input using the Si5338, but it isn't entirely clear that this is possible. Many clock generators and buffers from SiLabs that use the "Any-Format Input" claim that the input isn't compatible with AC or DC-coupled LVCMOS input when using VDD = 1.8V. The Si5338 doesn't use the "Any-Format Input" or spec LVCMOS as an input, but it allows a DC-coupled CMOS input clock and the voltage swing minimum voltage is 0.8V, which appears to be compatible with a 1.2V LVCMOS input. So to ask my question simply: will the Si5338 successfully generate a clock output from a 1.2Vpp LVCMOS input? From the datasheet, it appears possible, but I would like to confirm.
Additionally, is there any advantage of running my 1.2V LVCMOS input into the AC-coupled differential inputs over the DC-coupled single-ended input? I believe my signal meets all of the specs for the single-ended input so I am inclined to use that input, however the input impedance is not specified and the differential input voltage swing is considerably lower.
Thanks - Ned
Hello, I am configuring an Si5332E-D-GM2 with i2c from an FPGA. I have a problem where a few Si5332s do not acknowledge the i2c transaction and do not configure. I tried both default i2c slave address 6A and 6B, along with every other slave address. VDD is 1.8V and the i2c is 1.8V with 2k pullups on SCL and SDA. I notice on the Si5332 that do not acknowledge, the first few SCL and SDA pulses are not pulled down fully as if they are being held up by the Si5332, please see attached image of o-scope showing this. Any help on this issue would be appreciated.
I was looking at the technical reference for the Si5345 to understand the input termination requirements for single-ended clock inputs at very low frequencies (8-10 KHz). The evaluation board capacitively coupled the inputs using 0.1uF capacitors, but I suspect this will not work well at such low speeds. The manual (section 5.2 Types of Inputs) describes both AC coupling ("Standard AC-Coupled Single-Ended (IN0-IN3)") and "DC-Coupled Pulsed CMOS only for Frequencies < 1MHz (IN0-IN3)". Initially I was going to 50 terminate and then AC couple with a 10 uF MLCC capacitor (1.3 ohm reactance nominal, probably 3-4 ohms at maximum bias voltage). However, the DC-coupled option for low frequency clocks looks like it might be an option as well.
Should I prefer one or the other? My input it a 5V TTL signal from a resonator with high Q, so the input should be a relatively narrow period square wave. I was going to attenuate it down to 0-3.3V for driving the input clock and then connect with a 50 ohm SMA cable.
Thanks for any guidance!
Hello. I have a si5324 chip with a 114.285 MHz crystal on the XA/XB pins, and a 156.25 MHz clock on the CKIN1 pins. I am trying to generate a "cleaned" 156.25 MHz clock on the CKOUT1 output pins. CKIN2 and CKOUT2 are left floating.
I used the DSPLLsim tool to generate the register settings, in which I have successfully configured and verified. However, I'm getting the following results when I read the status registers:
LOSX_INT = '0'. NORMAL LOS1_INT = '0'. NORMAL LOS2_INT = '0'. NORMAL LOL_INT = '1'. PLL NOT locked FOS1_INT = '0'. NORMAL FOS2_INT = '0'. NORMAL DIGHOLDVALID = '0'. Waiting on more samples LOL_FLG = '1'. PLL Not Locked FOS1_FLG = '0'. NORMAL FOS2_FLG = '0'. NORMAL ICAL = '0'. NORMAL
Also, I am continually writing a 0x00 to register 132 to clear the latched status bits. I have waited quite a long time
for the PLL to lock (it's at least 30 min now), but it never does.
These are the settings generated from the DSPLLsim tool:
#HEADER # Date: Tuesday, March 30, 2021 3:01 PM # File Version: 3 # Software Name: Precision Clock EVB Software # Software Version: 5.1 # Software Date: July 23, 2014 # Part number: Si5324 #END_HEADER #PROFILE # Name: Si5324 #INPUT # Name: CKIN # Channel: 1 # Frequency (MHz): 156.250000 # N3: 4993 # Maximum (MHz): 177.187500 # Minimum (MHz): 151.562500 #END_INPUT #INPUT # Name: CKIN # Channel: 2 # Frequency (MHz): 114.285688 # N3: 3652 # CKIN2 to CKIN1 Ratio: 14285711 / 19531250 # Maximum (MHz): 129.599188 # Minimum (MHz): 110.856449 #END_INPUT #PLL # Name: PLL # Frequency (MHz): 5000.000000 # XA-XB Frequency (MHz): 114.285000 # f3 (MHz): 0.031294 # N1_HS: 8 # N2_HS: 8 # N2_LS: 19972 # Phase Offset Resolution (ns): 1.60000 # BWSEL_REG Option: Frequency (Hz) # 5: 4 # 4: 9 # 3: 18 # 2: 37 # 1: 78 #END_PLL #OUTPUT # Name: CKOUT # Channel: 1 # Frequency (MHz): 156.250000 # NC1_LS: 4 # CKOUT1 to CKIN1 Ratio: 1 / 1 # Maximum (MHz): 177.187500 # Minimum (MHz): 151.562500 #END_OUTPUT #CONTROL_FIELD # Register-based Controls # FREE_RUN_EN: 0x1 # CKOUT_ALWAYS_ON: 0x0 # BYPASS_REG: 0x0 # CK_PRIOR2: 0x1 # CK_PRIOR1: 0x0 # CKSEL_REG: 0x0 # DHOLD: 0x0 # SQ_ICAL: 0x1 # BWSEL_REG: 0x5 # AUTOSEL_REG: 0x0 # HIST_DEL: 0x12 # ICMOS: 0x3 # SLEEP: 0x0 # SFOUT2_REG: 0x7 # SFOUT1_REG: 0x7 # FOSREFSEL: 0x2 # HLOG_2: 0x0 # HLOG_1: 0x0 # HIST_AVG: 0x18 # DSBL2_REG: 0x1 # DSBL1_REG: 0x0 # PD_CK2: 0x0 # PD_CK1: 0x0 # FLAT_VALID: 0x1 # FOS_EN: 0x0 # FOS_THR: 0x1 # VALTIME: 0x1 # LOCKT: 0x1 # CK2_BAD_PIN: 0x0 # CK1_BAD_PIN: 0x1 # LOL_PIN: 0x0 # INT_PIN: 0x1 # INCDEC_PIN: 0x1 # CK1_ACTV_PIN: 0x0 # CKSEL_PIN: 0x0 # CK_ACTV_POL: 0x1 # CK_BAD_POL: 0x1 # LOL_POL: 0x1 # INT_POL: 0x1 # LOS2_MSK: 0x0 # LOS1_MSK: 0x0 # LOSX_MSK: 0x0 # FOS2_MSK: 0x0 # FOS1_MSK: 0x0 # LOL_MSK: 0x1 # N1_HS: 0x4 # NC1_LS: 0x3 # NC2_LS: 0x3 # N2_LS: 0x4E03 # N2_HS: 0x4 # N31: 0x1380 # N32: 0xE43 # CLKIN2RATE: 0x3 # CLKIN1RATE: 0x4 # FASTLOCK: 0x1 # LOS1_EN: 0x3 # LOS2_EN: 0x3 # FOS1_EN: 0x0 # FOS2_EN: 0x0 # INDEPENDENTSKEW1: 0x0 # INDEPENDENTSKEW2: 0x0 #END_CONTROL_FIELD #REGISTER_MAP 0, 54h 1, E4h 2, 52h 3, 15h 4, 12h 5, EDh 6, 3Fh 7, 2Ah 8, 00h 9, C0h 10, 08h 11, 40h 19, 29h 20, 35h 21, FCh 22, DFh 23, 18h 24, 39h 25, 80h 31, 00h 32, 00h 33, 03h 34, 00h 35, 00h 36, 03h 40, 80h 41, 4Eh 42, 03h 43, 00h 44, 13h 45, 80h 46, 00h 47, 0Eh 48, 43h 55, 1Ch 131, 1Fh 132, 02h 137, 01h 138, 0Fh 139, FCh 142, 00h 143, 00h 136, 40h #END_REGISTER_MAP #END_PROFILE
Are there any mistakes in the configuration?
One more note: If I read the I2C registers immediately after I write to them, the verify comes back good (the values match), however, after I've run the calibration, the values are automatically changed in the following registers: 31, 32, 36, 42. Is this normal and expected?
Our application uses the CLK0 and CLK1 outputs of a 5351A chip (on a third party PCB) as local oscillators in our ham radio application. These clocks operate at 106.8 MHz and 107.4 MHz, with a reference clock of 19.2 MHz driving the PLL X0 input. We are seeing very high spur content from both of the clock outputs, despite efforts to implement integer division synthesis in the PLL feedback loop as well as in the output clock divider chains. We are using an Arduino Pro Mini to program the 5351A (see the hardware photo).
The 2nd and 3rd photos shows the spectrum from one of the clock outputs. The first of these was obtained using a 19.2 MHz clock with the PLL feedback integer mode disabled and the 2nd obtained with a 4.8 MHz clock with PLL feedback integer mode enabled (106.8 MHz x 8 and 107.4 MHz x 8 are both integer multiples of 4.8 MHz). The Arduino programming file used to obtain each of these photos (with the same filename) is also shown for reference. We are constrained to use a 19.2 MHz clock or some integer divisor of it by its use elsewhere in our radio system.
Could someone please advise me what might be wrong?
Thank you very much!
Oliver Barrett KB6BA
We are currently using Si5348 as a network synchronizer in our network edge systems. we also want to use Si5389B as an additional network synchronizer to support more peripherals. We are unable to find IBIS models for Si5389 from the above link "https://www.silabs.com/support/resources.ct-software.p-timing?query=IBIS". I request you to provide us the IBIS simulation model for Si5389B to move forward with our design.
On a side note, since Si5348B and Si5389B belong to the same family of network synchronizers and have the same input and output frequencies, by any chance do they have the same input and output buffers so that we can use the si5348 IBIS model for Si5389 as well.
Thanks and Regards,
I'm trying to configure an Si5340 with I2C. The I2C_SEL is floating, which I heard is OK since it's supposed to have an internal pullup. I see a SiLabs Si5430 reference design that uses an --external-- pull up to drive an LED on the I2C_SEL. The forum post shows Si5394 I2C_SEL pin which --internal-- pullup (https://www.silabs.com/community/timing/forum.topic.html/si5394_i2c_sel_pinlevel-i1KS).
Other I2C devices program OK. But Si5430 won't respond.
Can someone verify this Si5340 has an internal I2C_SEL pullup?
Can someone help me understand the definition of "HF RMS" Jitter as it pertains to the the PCIe Spec and the SILabs Clock Jitter Tool?
Reading Rev 5.0, Ver 0.9 01/07/21 of the PCIe Card Electromechanical Spec, Table 2-3 denotes 200fs of allowable Rj RMS jitter
I would like to understand the differences between the "HF RMS" and "LF RMS" values shown in the output of the SILabs Clock Jitter Tool (circled in the exert below).
Table 4-24 of the Rev 5.0, Ver 0.9 01/07/21 of the PCIe Card Electromechanical Spec states Rj is assessed 1.5MHz - 10MHz as low frequency and the upper limit is 1GHz. Does this mean that the SILabs clock jitter tool (or any other tool) assess a measured period trend and calculates jitter within two distinct frequency ranges, (a) Low Frequency between 1.5 and 10MHz and (b) 10MHz to 1GHz High Frequency?
I am currently using the Phase INC/DEC function with the Si5338.
1) The datasheet says that the accuracy of phase steps is "20ps" MAX.
However I have measured the repeatability of these phase steps to be <4ps RMS. Also, the granularity is more of the order of 3ps.
2) And for example on this post, we have an example of how to set up a 20ps phase step size
(which is questionable if the phase step accuracy is 20ps. You would not want to have 0ps steps when you programmed 20ps. )
-> So my question is: why is the quoted accuracy of 20 ps while it seems to perform much better? what is the limitation (temperature effects, ageing, ... ? )? Is there a Silabs alternative which would achieve 3ps?
We have a board with Si5347D-D on it.
It works fine, but we haven't find how to force one (or all) PLLs to go into freerun mode by registers access?
NOT holdover, 100% freerun with frequencies sourced from external XO.
This is required when input have some frequency and it can be locked, but the source of frequency is wrong and should be replaced by XO' sourced frequency.
We have SPI access to Si5347D chip, so best way is to find what registers should be changed to give us what we need.
Thank you in advance for any help.
We are using si5342, the input frequency is determined by incoming data, and so is the output frequency.
I prefer not to use ClockBuilder Pro and create all the options - since there are many.
Is there a way to calculate all the registers' values and set them on run time? We don't mind doing a soft reset or other procedure to make the effect.