HI, guys,

  I meet a strange question about SI5338A .

  I layouted my test demo, I  used 25MHz input reference to IN3, VDD & VDDO are both 1.8V.  The device was in normal I2C write & read communication. 

  In my test, I programmed the device to output 100MHz LVDS clock  in both 4 channels, the register configurations were made by the the CBPro Tools. 

  During the  initialization process, I need to configure the PLL lock status, to see if the PLL is locked.  

  But I found that the code was stucked in the while loop as follows

//make sure the device locked by checking PLL_LOL and SYS_CAL
reg = I2C_ByteRead(218) & LOCK_MASK;
while(reg != 0){
reg = I2C_ByteRead(218) & LOCK_MASK;
}

I check the value of register 218, it was 0x09, which means SYS_CAL was assert 1 all the time.   

I also checked other register values wrote to the device before this loop and they are OK. 

So, I tried to ignore this and continued to complete the rest registers, it was no use. No outputs turned on ch0~ch3.

Is there anybody who have even been in the same situation ?

Thanks.

hello,

Four channel clocks are configured with clock builder as follows:

channel 0 ：  10khz

channel 2：   500khz

channel 4:      3 Mhz

channel 6       15Mhz

But the actual output frequency is as follows:

channel 0 ：  12.42khz

channel 2：   622.5khz

channel 4:      3.74Mhz

channel 6       18.66Mhz

The frequency of all channels is too high。

Thank you for your answers。

 

 

According to the datasheet the Si5336x can provided 1.2V or 1.5V output with the appropriately configured divider at the output. The datasheet only specifies the divider for a 1.8V VDDO. I have an application where I'd like to use 3.3V for my VDDO but I need 1.2V output level.  What would the resistor configuration be? Can you explain the reasoning behind the resistor selection? 

I would like to find a chip that can clean up pcie diff clock jitter,but i can't find this application.I can't find attenuation chip dataheet about hcsl(pcie clk) input description

Hello Silicon Labs,

 

Looking for the appropriate sample rate, memory depth/record length, and band width for a tektronix scope to render the correct input for the PCIE clock jitter tool appiication.

 

 

 

Thanks,

Benny

 

In the documentation it does not label the pins on J20, and I need to know which ones are 4 and 6, and 1,2,7, and 8. It labels the other pins, like on J12 and J13 for example, but there isn't a pattern to it. For example, J12 pins are 1,2,3 from top to bottom, and the J13 pins are 1,2,3 from bottom to top. Also on the board, it doesn't say which J20 pins are ground, SCL, and SDA, which is what I need to know. Is there anyway I can find out which pins are which without guessing and checking?

Hello,

  I am having difficulty finding a socket (spring latch type perhaps) for the SI570 series devices, can you point me in the direction of one/some?

Thank you,

-James

Hi,

DS Rev. 1.0, chap. 2.3: " To optimize jitter and duty cycle performance, use the circuit in Figure 2.3 AC-Coupled, Single-Ended (LVCMOS) Input Termination".

Is the recommendation to optimize jitter: a) to AC-couple, b) to use external resistors instead VREF  or c) to AC-couple and to use external resistors instead VREF ?

Please note we are focusing on jitter and less on duty cylce performance.

Thank you for your help!

Hello,

I am trying to load a waveform file that looks like it should work but I get the following message.

I have attached the file. I can't tell from this error message what I need to adjust.

I see the Si5351A now comes in QFN16 package -

Can Silabs advise on Price & Availability ?

Hi,

our company is considering to use the Si5341 or Si5340 as a clock generator for reflectometric purposes, thus requiring sub-picosecond clock alignment. It would be configured so that each output would be configured the same with one exception - the delay between them. Regarding this usage, we have two questions:

1. The datasheet states that the delay step is Tvco/256 which is about 0.3 ps. However, in other place it states this: "A soft reset will align the outputs to within ±100 ps of the expected value based upon the Nx_DELAY parameter." (Si5341/40 Rev D Data Sheet, Rev. 1.0, page 11) Is this alignment tolerance deterministic (for example caused by manufacturing tolerances) - is it the same for a specific unit each time it is reset? Or is it random and changes after each reset? It would seem logical to us to be deterministic, because otherwise it would make no sense to make it possible to set the delay such precisely (lowest 8 bits of the delay would be unusable due to the ±100 ps skew tolerance). In the former case, it would be usable for us. In the latter case, we would have to resort to some other timing product.
2. When the soft reset is asserted, what exactly happens? Does it cause the PLL to unlock and re-lock? Our usage would be as follows: Configure the Si534x initially, perform measurement with that setting, change delay setting, assert soft reset, perform measurement and repeat this sequence of operations. How much time would each configure-reset-stabilise cycle require? If it took the 15-150 ms required for PLL locking, we would again have to resort to some other timing product.

//EDIT_1: I have thought about the problem with the delay tolerance. If it is true that it is ±100 ps, it means that two outputs may be offset by 200 ps. Since the Si5341A/C is rated up to 1028 MHz, that means at the highest frequency setting, two outputs offset by 200 ps (maximum allowed by the tolerance field) would have phase difference of 74 degrees. Since the Si5341 is meant to be used as clock source for FPGAs, processors, memories etc., such a large phase difference would render it next to unusable. Therefore, I believe that the delay tolerance should be much smaller. Could you please explain this to us?

//EDIT_2: OK, so according to https://www.silabs.com/community/timing/forum.topic.html/si5341_r_dividerres-WeGz, it is true that outputs of inidividual MultiSynths may be offset by as much as 100 ps. Again, what is the intended use of the delay block? I would expect it to be used to fine-tune delay between devices on PCB. However, as it seems, it may break things even more than when not used, since it seems to be non-deterministic (at least from the point of view of a user of Si5341).

Thank you in advance for your response,
Ing. Petr Polasek
R&D HW Engineer

Hello!

I work with Si5341D and now write some configuration software.

I see in this document https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf what VCO range is 13.5G to 14.4 G (page 26)

In this documenut https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf i see (page 32)

The output N divider can be changed from its minimum value of 10 to its maximum value of 409

I try to generate some clock design and see some strange things

Frequency Plan
==============
Priority: maximize the number of low jitter outputs

Fpfd = 48 MHz
Fvco = 14.4 GHz
Fms0 = 1.8 GHz
Fms1 = 960 MHz
Fms2 = 260 MHz
Fms3 = 420.768 MHz
Fms4 = 347.43 MHz

P dividers:
   P0  = Unused
   P1  = Unused
   P2  = Unused
   P3  = Unused
   Pxaxb = 1

M = 300
N dividers:
   N0:
      Value: 8
      OUT3: 150 MHz
      OUT6: 100 MHz
   N1:
      Value: 15
      OUT0: 40 MHz
      OUT5: 40 MHz
      OUT7: 80 MHz
      OUT8: 160 MHz
      OUT9: 120 MHz
   N2:
      Value: 55.3846153846153846... [ 55 + 5/13 ]
      OUT4: 65 MHz
   N3:
      Value: 34.2231348391512662... [ 34 + 326/1461 ]
      OUT1: 70.128 MHz [ 70 + 16/125 MHz ]
   N4:
      Value: 41.4471979967187634... [ 41 + 5179/11581 ]
      OUT2: 57.905 MHz [ 57 + 181/200 MHz ]

Its generated by clock builder 2.43

I not understood what N can be in range 10 to 4095, or may be document not actualy?

Second part 

Frequency Plan
==============
Priority: maximize the number of low jitter outputs

Fpfd = 48 MHz
Fvco = 13.2 GHz
Fms0 = 80 MHz

P dividers:
   P0  = Unused
   P1  = Unused
   P2  = Unused
   P3  = Unused
   Pxaxb = 1

M = 275
N dividers:
   N0:
      Value: 165
      OUT0: 40 MHz
      OUT1: 40 MHz
      OUT2: 40 MHz
      OUT4: 40 MHz
      OUT5: 40 MHz
      OUT6: 40 MHz
      OUT8: 40 MHz
   N1:
      Unused
   N2:
      Unused
   N3:
      Unused
   N4:
      Unused
 

But 13.2G is less 13.5G document not actual too?

Can your say real range of VCO and N deviders?

 

Hi, Team:

In SI5347 datasheet, it describe that the DCO mode is available in both free run and locked mode, while in the reference manual, it said DCO mode isn't available in free run mode or holdover mode. Would you clarify the description?

In the FAQ question list, the file mentioned the DCO mode need a reference input? Here the reference clock is  on the INx pin clock, not the XA/XB, right?

In our application, we want the control the output frquency by step in 10ppt when the INx reference clock isn't ready? Can we use DCO mode or you have other potential solution?

Thanks!

 

Hi 

I`m new in this field.

Please advice what is customize part, is it mean I need to pre configure it by ClockBuilder Pro and generate new part number to order,

or is it part which I can configure it in my board while working when needed by I2C.

Thanks