I am using a board that I did not design, but I need to change the Si570 output.
SiLabs 570 BAB000544G oD07x8628+
The lookup tool is not finding anything
I think based on datasheet the device is a 50ppm version marked with 000544 so I surmise that it has f0 = 544MHz
My register readback [x07-x0C] is 01 C2 BC 39 A3 DB
Based on these I decode HS_DIV 4 and N1 7
Decode RFREQ 2BC39A3DB = 43.7641
So Fxtal = 348.048MHz
Is this a reasonable Fxtal (the examples in docs have 156MHz, etc)?
Has anyone used an Arduino to load the registers on an Si534x chip? If so, are you willing to share the code or any tips/tricks/issues? I'd like to avoid re-inventing the wheel if possible.
Out 9 is configured as the input to ethernet phy as 25Mhz. the issue is ethernet doesnot work.
The same circuit with the crystal oscillator of 25Mhz as input to ethernet phy works fine.
Can I know how to solve the issue?
I have some questions about Si5317.
My requirement is as follows:
Output of FPGA(about 20MHz ,LVCMOS3V3) is connected to CKIN+, that is, the input source to pin CKIN+ is very dirty. And I am planning to make it clean by using Si5317?
My questions are:
Inside of loop Bandwidth, the phase noise of PLL output depends on PLL synthesizer and ref.
Outside of loop Bandwidth, the phase noise of PLL output depends on phase noise of VCO.
Is it similar in Si5317? If I set loop BW enough low, I can get a clean source?
3. As follows is a picture of Si5345:
How the crystal connected between XA and XB impact the jitter performance of the output signal? Is crystal a part of VCO? But how? Can you supply more details about connections between OSC and VCO?
4.If I didn’t connect crystal or clock on XA and XB,can Si5314 work since I already supply CKIN+?
first of all, sorry for a new thread on this topic, but I don't understant exactly how to proceed...
The FPGA receive clocks and data from an external chip (on another demo board) with the following charcteristics:
1) Clk freq is 60MHz.
2) The data output delay from clock varies from 2 to 5 ns.
3) The frequ is 60MHz
These datas come from chip datasheet but (obviously) don't take into account board delays...these relations are valid only for the chip...
I've read many docs on timequest but the topic is still not completely clear(the syntax could be wrong):
1) need to generate the clock inside fpga
create_clock -name fpga_clk -period 16.6 [get_ports clk_in]
2) need to generate external clock (for the chip providing clock) ... (need some phase relationship???)
create_clock -name ext_clk -period 16.6
3) add I/O constraints relative to ext_clk from datasheet
set_input_delay -clock ext_clk -max 5.0 [get_ports din*]
set_input_delay -clock ext_clk -min 2.0 [get_ports din*]
My questions are:
Are those the only constraints I need? How take into account the board delays?
Altera docs start from kwnoledge of board delays and relationship between clock and data...or they use the skew approach...I don't understand how to use my datasheet parameters to implement one of the two methods...
You know, I need to interface an ULPI transceiver to my FPGA...the transceiver generates clocks and data for the fpga as in the attach...(clock out and data out)
Yesterday i read a very interesting article discussed the influencing factors of clock in FPGAs http://www.kynix.com/Blog/439.html, said it could be useful to analysis a basic model of synchronous design using a single clock with the help of timing diagram, what exactly this is mean?
As you can see data follows the rising edge fo clock after min 2 ns and max 5 ns....(Pick up if you need this: )
I suppose that this should be the input delay (min, max) to impose if we hadn't the delays for the links between transceiver and fpga...this delays are not neglectable and must be taken into account but how???
I could use an FPGA centric method (skew method) to avoid taking into account these delays...but I don't understand how to proceed in this direction...i.e. not knowing board delays means that I don't the relation between clock and data at FPGA input...therefore I don't know how to proceed...
I need help
THX in advance
I like to know more about the Si549 ADPLL_DELTA_M registers, how are they interact with the VCO registers?
In the Si549 datasheet there is a value, 0,0001164, to convert a delta output freqeuncy PPM value to the ADPLL_DELTA_M register's, that value is not a (negative) power of two. How is the register connected to the DCO when it is not a power of two, maybe analog?
Thanks for reading
I have a few chips on a single I2C bus, one is the Si5342D. When addressing other chips on the bus, the SCL line is held low at the end of the chip address byte transfer. If I reset the parts that have a reset, including Si5342, and address a device without a hardware reset, the problem goes away. Has anyone seen this happen with their Si534x designs?
I installed on my board the Si53340 and Si53344 chips. in datashit for this chips is indicated that it is possible to supply a supply voltage of 1.8, 2.5 or 3.3 Volts. There will be a little bit different matching on the signal input, it's not critical. It was easier for me to apply 3.3 volts because of the common power bus in the compactPCI system. And when I switched on my board, I felt that all of my 10pcs Si53340 chips and 4pcs Si53344 chips are heated pretty seriously. A 3.3 Volt power is decreased to 3.2 at the reference point and even down to 3.1 near the power supply pins of these chips! I had the opportunity to throw the power to 1.8 Volts (look at the picture, as far as it's not beautiful). Immediately, the voltage drop of 3.3 Volts disappeared. The voltage 1.8 V became 1.77 V, well, that's fine. The chips stopped warming themselves. The output characteristics of the clock frequency so far suit me. Tell me, what's wrong? Why is it because of the 3.3 Volt power supply your chips work so heat? The 3.3 V power supply is installed at 30 amperes (LMZ31530). Even 14 chips do not have to squander it in normal mode! While the source in 1.8V to 10 amperes (LMZ31710) almost does not drain. Can you have Errata on these chips? I have not found it on your website. The current consumption measurement is indicated for the voltage Vdd = 3.3 V in datashit. Most likely for 1.8 V the current consumption should be less. But it's not a mistake to power from 3.3V. So why does the voltage drop to 3.1 V? Chips were re-soldered, changed, the central leg GND was checked, soldered. I will attach a picture, including a PCB.
I am needing to measure phase noise of 160 MHz carrier (differential LVDS) out to a E5052B (or equivalent) Phase Noise Analyzer. I see in most datasheets like Si533xx series that an external balun (Tektronix PSPL5310R) was used to transform the differential output to a single-ended input for the PNA. Has this balun been widely used for the PNA measurement? Is there some SMT type balun with similar performance to the PSPL5310R that I could solder directly onto our PCB? ...or is that a bad idea? I did see a Pulse Electronics CX2156 SMT that was referred to in AN862. Any guidance would be appreciated.