I downloaded the new version 4.1 PCIe Clock Jitter Tool released yesterday and this tool is not able to load the .trc waveform file. However, the previous version 4.0 works without any problems with the same file. Please check.

I found in the ClockBuilder SW Si53358/4/2B clock buffers that are very suitable for my application. As I see in the SW, these components can be programmed to divide an input clock by any number from 1 to 63, but I can't find any info about clock dividers in the datasheet.

1. Do Si5335xB devices really support clock division by any integer ?

2. If yes - what is outputs duty cycle in case of odd divider (for example 3) ?

3. Are these parts available for order/samples?

Hi,

 

I have an existing PCB with Si5324. 

The Si5324 has a 114.285MHz xtal connected to its XA and XB pin. 

Can the Si5324 be configured as a clock generator?

Can it be configured to generate a 148.5 MHz clock? 

I've read about it in the following address: https://www.silabs.com/community/timing/forum.topic.html/can_si5324_be_useda-jSSl

I've tried using the "Si5324_156M250_FreeRun.txt" file, but it did not help.

Please advise.

 

Thanks,

Andrei

I am doing reference clock jitter analysis using the Si Labs clock jitter tool. I see that the results are very different when using a waveform input file and when using a time interval input file. What are the pros and cons of using either method? The tool supports both, but which method do you recommend and why? Please let me know. Thanks!

Part NO: SI5332E-D-GM1

Playing around with CBPro, I see that there is a Frequency Select option (the Multi Synth outputs, not the integer dividers) which can be either controlled through i2C writes or by toggling one on the GPIs. Have many questions regarding its operation and speed.

 

1. How large a frequency change is possible with this? I need the two profiles to be anywhere within 100 - 200 MHz range, 100 KHz steps would be nice.

2. What is the time taken to switch between the frequencies, once I toggle the GPI? Something below 100 uSecs would be ideal.

3. How slow would updating the profile over i2c be? Can I in effect have a large number of profiles (even if switching between them would be too slow)?

3. Can using this feature possibly worsen the jitter in some way?

4. Is this the same DCO feature mentioned in Si5341/40 datasheets or completely different?

5. If such fast switching isn't possible with this feature, can I in some way combine two outputs but OE disable one of them as required? (OE switch on delay was mentioned as less than 20us in the datasheet).

The two profiles seem to work fine for large frequency changes (85.74 MHz - 165.34 MHz and so) but fails freq planning when I try something like this: 85.7432 MHz and 165.3456 MHz. The error it gives is: "Cannot store Frequency Select solution within the range of N0". So I am guessing it has something to do with the numer/denom limits? I don't really need such offsets but would like to know the limitations of this.

 

Edit: This does answer some details and mentions the feature as DCO but with a different process. But doesn't clarify the "settling" time (is it instantaneous once the dividers banks are switched over?). https://www.silabs.com/community/timing/knowledge-base.entry.html/2019/10/29/si5332_dco_processintroduction-Swzo.

Hello Sir/Mam

we need MTBF and FIT of Part SI5384B-D00100-GM

Hello,

I don't find in si515 i2c device, any description of the registers (for the i2c access),

Which document describe these registers ?

Thank you

It is said "The input-to-output skew is not controlled. External circuitry is required to control the input-to-output skew".

In my application, it is strictly required that the input-to-output skew shall be less than 0.1ns.  How to add external circuitry to control it?

In the application, the input reference clock is 1MHz, and it is stable.  And I need to frequently write setting to CLAT[7:0] and FLAT[14:0] to adjust the skew.

Onec CLAT[7:0] and FLAT[14:0] are written, the DSPLL would lose the lock status or not?  If yes, the lock time will be the value as datasheet indicating?

My local FAE also cannot seem to find what I would have thought is a basic function.  I have a custom part number with SiLabs for a 5332 part.  I have received my first samples of the parts.  I simply want to load those parts in the programming dongle and verify the programming is the same as the project file I supplied to SiLabs.  The part does show the correct design ID, but I would like to 100% verify.

 

Thanks for any insight!

Hi,

I need design a in-circuit programming circuit for Si5340 so I can program it use a mcu, My question is: Do I need connect a 48 MHz crystal to Si5340 XAXB pin and connect IN_SEL1,0 pins to select XAXB as input to get the device running, then I can programming it through I2C/SPI?

Thanks.

 

Hi,

In the Si5341, Si5340 Rev D Family Reference Manual, chapter 14.1, the last sentence is:

See the on-line lookup utility to access the default configuration plan and register settings for any base OPN.

I think I can find the default registers value for the blank device in the on-line lookup utility, but the url jump to an error page, could you plese give me a right url?
The bad url is https://www.silabs.com/products/clocksoscillators/pages/clockbuilderlookup.aspx

 

Thank you!

Hi,

I am trying to program the si570CBC000306DG via i2c from an Intel Cyclone V FPGA. I seem to be able to read and write from the si570, as it acknowledges the by pulling the SDA line when I write to it. However, the output frequency remains at the start-up freq. and the DCO never freezes. I am following the protocol described in the datasheet, freezing the DCO (Reg 137, 0x10) -> Writing to Reg 7-12, Unfreezing the DCO (Reg 137, 0x0) -> Asserting NewFreq (Reg 135, 0x40). I have read data from the si570 prior to executing this procedure to calculate fxtal for my new freq. calculations. I have attached screenshots of the SDA and SCL lines that are being sent to the si570. My SCL and SDA lines seem to be correct with respect to the datasheet and i2c standard. I have also tried switching out the si570 but have had no success. Have I overlooked something that is causing my oscillator to be stuck at the default freq?

Write Procedure Waveform:

DCO Freeze:

Reg 7-12 Data:

Unfreeze DCO -> Assert NewFreq

Read Procedure Waveform:

NACK:

PCIe Clock Jitter Tool V4.0 does not calculate Pk-Pk Jitter for GEN1 and compliance result is always N/A, see attachment. 

Before I worked with PCIe Clock Jitter Tool V3.0 and I always get a result for GEN1 Pk-Pk Jitter.

I tried with PCIe .trc data I collected some time ago and with V3.0 I get a result but with V4.0 not.

What may be the root cause?

Dear community,

I am not able to find an option for setting output skew (NX_delay) in new (2.35) Clock Builder Pro.

In 2.27 it was step 9 Input/Output Skew control.

Am I missing something obvious?

Thanks in advance,

Konrad