ARM's Flagship Cortex-M Class Processor
The ARM Cortex-M3 processor offers superior efficiency and flexibility and is specifically developed for response and power sensitive applications. The EFM32™ 32-bit MCUs use the Cortex-M3's low power and high performance abilities in combination with Silicon Labs' unique low power peripherals to create a superior low power embedded systems platform.
- 32-bit Cortex-M3 designed for low power operation
- High power efficiency with Thumb®-2 instruction set
- Small core footprint with integrated power mode support
- Cortex-M3 delivering 1.25 DMIPS/MHz
- Separate data and instruction bus
- High code density and performance with Thumb-2 instruction set
- Excellent clock per instruction ratio
- Nested Vectored Interrupt Controller (NVIC) for outstanding interrupt handling
- Superior math capability
Thumb-2 Instruction Set Architecture (ISA)
Cortex-M3 supports 16- and 32-bit instructions available in the Thumb-2 instruction set. Both can be mixed without extra complexity and without reducing the Cortex-M3 performance. Hardware divide instructions and a number of multiply instructions give EFM32 users high data-crunching throughput.
3-stage Pipeline Core Based on Harvard Architecture
The ARM Cortex-M3 3-stage pipeline includes instruction fetch, instruction decode and instruction execution. Cortex-M3 also has separate buses for instructions and data. The Harvard architecture reduces bottlenecks common to shared data- and instruction buses. Quickly Servicing Critical Tasks and InterruptsFrom the low energy modes, EFM32's Cortex-M3 is active within 2 µs and delivers 1.25 DMIPS/MHz on the Dhrystone 2.1 Benchmark. The NVIC is an integral part of the Cortex-M3 processor and ensures outstanding interrupt handling abilities. It is possible configure up to 240 physical interrupts with 1-256 levels of priority, and Non-Maskable Interrupts further increase interrupt handling. For embedded systems this enhanced determinism makes it possible to handle critical tasks in a known number of cycles.
Reducing the 32-bit Footprint
The Cortex-M3 has a small footprint which reduces system cost. High 32-bit performance reduces an application's active periods, the periods where the CPU is handling data. Reducing the active periods increases the application's battery lifetime significantly, and the EFM32 can spend most of the time in the efficient low energy modes.
ARM Cortex-M3 Based MCUs
|Family||Speed (MHz)||Flash (kB)||RAM (kB)||USB||LCD||UART||USART||I2C||I²S||Packages|
||32||4, 8, 16, 32||2, 4||No||Yes||2, 3||1, 2||1||1||BGA48, QFN24, QFN32, QFN64, QFP48, QFP64|
||32||16, 32, 64, 128||8, 16||No||Yes||0, 1||2, 3||1||0||BGA112, QFN32, QFN64, QFP100, QFP48, QFP64|
||40||128, 256, 1024||32, 256||No||No||0||2, 4||1, 2||1, 2||BGA125, QFN32, QFN48|
||48||64, 128, 256||32||Yes||Yes||5, 7||3||2||1||BGA112, BGA120, CSP81, QFN64, QFP100, QFP64|
||48||512, 1024||128||Yes||Yes||5, 7||3||2||1||BGA112, BGA120, QFN64, QFP100, QFP64|