Si5348/83/84/88/89 Network Synchronizer Clocks
The Silicon Labs network synchronizer clocks lead the industry in jitter performance while offering low power consumption. With up to three integrated DSPLL® devices and small package sizes, these devices reduce complexity and PCB footprint requirements for timing synchronization. Our network synchronizer clocks are ideally suited for SyncE/SONET/SDH timing card and pizza box applications, as well as wireless communication systems and data center switches.
Each DSPLL is individually configurable as a SyncE/SONET/SDH PLL, IEEE 1588 DCO with support for 1PPS/1Hz, or a general-purpose PLL for processor or FPGA clocking. Legacy SETS systems can also use these devices to achieve Stratum 3/3E compliance.
The Si5388/89 clock has embedded IEEE 1588 servo loop processing and when combined with the available IEEE 1588 host software stack, it forms a complete IEEE 1588 synchronization solution for pizza box applications, wireless 5G communication systems, and data center switches.
- Up to three independent DSPLLs in a single IC supporting flexible SyncE/IEEE 1588 and SETS architectures
- Si5388/89 clock has embedded IEEE 1588 servo loop processing and when combined with the available IEEE 1588 host software stack, it forms a complete IEEE 1588 synchronization solution.
- Each DSPLL generates any output frequency from any input frequency
- Support for 1PPS/1Hz input and output frequencies
- Excellent jitter performance of 100 fs RMS
- Programmable loop bandwidth per DSPLL as low as 0.001Hz
- Synchronous, free-run and holdover modes
- Automatic/manual hitless switching
- Status monitoring: LOL, LOS, OOF
- Pin or software controllable DCO on each DSPLL with resolution to 1ppt/step
- Meets the requirements of:
- ITU-T G.8262.1 (Enhanced SyncE) eEEC
- ITU-T G.8273.2 T-BC, T-TSC
- ITU-T G.8262 (SyncE) EEC Options 1 & 2
- ITU-T G.8262.1
- ITU-T G.8261
- ITU-T G.812 Type III, IV
- ITU-T G.813 Option 1
- Telcordia GR-1244, GR-253 (Stratum 3/3E)
|Part Number||Customize||Data Sheet||Dev Kit||Description||Control||Reference Inputs||Clock Outputs||Input Frequency min (MHz)||Input Frequency max (MHz)||Output Frequency min (MHz)||Output Frequency max (MHz)||Output Format(s)||Phase Jitter (RMS) (ps)||VDD (V)||VDDO (V)||Loop Bandwidth Min (Hz)||Loop Bandwidth Max (Hz)||Package Type||Package Size (mm)||Clock Generators||Jitter Attenuating Clocks||Synchronous Ethernet/1588||PCI Express Clocks||4G/LTE Wireless Clocks||Intel x86 Clocks|
|Si5348-E-EVB||Network synchronizer and jitter attenuator||I2C/SPI||5||7||0.008||750||0.000001||350, 718.5||CML; HCSL; LVCMOS; LVDS; LVPECL||0.125||1.8 + 3.3V||1.8; 2.5; 3.3||0.001||4000||QFN64||9x9||No||Yes||Yes||No||No||No|
|Si5383-D-EVB||3-PLL network synchronizer with 1PPS in/out||I2C||5||7||0.000001||750||0.000001||350, 718.5||CML; HCSL; LVCMOS; LVDS; LVPECL||0.15||1.8 + 3.3V||1.8; 2.5; 3.3||0.001||4000||LGA56||8x8||No||Yes||Yes||No||No||No|
|Si5383-D-EVB||1-PLL network synchronizer with 1PPS in/out||I2C||5||7||0.000001||750||0.000001||350, 718.5||CML; HCSL; LVCMOS; LVDS; LVPECL||0.15||1.8 + 3.3V||1.8; 2.5; 3.3||0.001||4000||LGA56||8x8||No||Yes||Yes||No||No||No|
|Si5389-EVB||2-PLL Network Synchronizer clock for IEEE 1588v2||SPI||5||8||0.000001||750||0.000001||350, 718.5||CML; HCSL; LVCMOS; LVDS; LVPECL||0.105||1.8 + 3.3||1.8, 3.3||0.001||0.004||LGA64||9x9||No||Yes||Yes||No||No||No|
|Si5389-EVB||3-PLL Network Synchronizer clock for IEEE 1588v2||SPI||5||8||0.000001||750||0.000001||350, 718.5||CML; HCSL; LVCMOS; LVDS; LVPECL||0.105||1.8 + 3.3||1.8, 3.3||0.001||0.004||LGA64||9x9||No||Yes||Yes||No||No||No|
Contact Sales for Si5388/89 Data Sheets.
Silicon Labs Timing Solution for Xilinx Zynq® Ultrascale+™ MPSoC and RFSoC
The Xilinx® portfolio of Zynq® Ultrascale+™ MPSoC and RFSoC are families of scalable high-performance FPGA’s combined with System-On-Chip product variants allowing customers to address a wide range of applications and system requirements. The Zynq® family of devices utilize innovative technology to deliver lower total power consumption without sacrificing performance.
Xilinx choose Silicon Labs timing devices to support their MPSoC (ZCU102) and RFSoC (ZCU111) evaluation kits due to their flexibility and low jitter/phase noise enabling their customers to achieve industry leading performance with low power consumption.
Silicon Labs Timing Key Features for Xilinx Designs
- Si5389 Network Synchronizer clock supporting SyncE and IEEETM 1588v2
- Clock sold with internal IEEE 1588 servo software and protocol stack software software forming a highly integrated IEEETM 1588v2 solution.
- Meets ITU-T G.8262 (SyncE) Opt 1 & 2, G.8262.1 (eEEC), G.8261, and G.8273.2 (T-BC & T-TSC).
- Used with either MPSoC or RFSoC
- Si5388-SW IEEE 1588 Protocol Stack Software
- The Si5388-SW protocol stack on host processor software is paired with the Si5389 clock with internal IEEE 1588 servo software to form the most integrated IEEE solutions in the industry.
- Used in conjunction with Si5389 clock with either MPSoC or RFSoC
- Si5386 Wireless Jitter Attenuator
- Ultra-low noise design delivers high-performance JESD204B DCLK and SYSREF clock pairs and flexible any-rate clocks for non-CPRI clocks such as Ethernet clocks
- Used with RFSoC.
- Si5341 Clock Generator
- The Ultra-Low Jitter clock can synthesize a wide range of integer and non-integer related frequencies with sub-100 fs rms phase jitter performance with 0 ppm error for system reference clocks
- Used with either MPSoC or RFSoC.