Si5348/83/84/88/89 Network Synchronizer Clocks

The Silicon Labs network synchronizer clocks lead the industry in jitter performance while offering low power consumption. With up to three integrated DSPLL® devices and small package sizes, these devices reduce complexity and PCB footprint requirements for timing synchronization. Our network synchronizer clocks are ideally suited for SyncE/SONET/SDH timing card and pizza box applications, as well as wireless communication systems and data center switches.   

Each DSPLL is individually configurable as a SyncE/SONET/SDH PLL, IEEE 1588 DCO with support for 1PPS/1Hz, or a general-purpose PLL for processor or FPGA clocking. Legacy SETS systems can also use these devices to achieve  Stratum 3/3E compliance. 

The Si5388/89 clock has embedded IEEE 1588 servo loop processing and when combined with the available IEEE 1588 host software stack, it forms a complete IEEE 1588 synchronization solution for pizza box applications, wireless 5G communication systems, and data center switches.

Features

  • Up to three independent DSPLLs in a single IC supporting flexible SyncE/IEEE 1588 and SETS architectures
  • Si5388/89 clock has embedded IEEE 1588 servo loop processing and when combined with the available IEEE 1588 host software stack, it forms a complete IEEE 1588 synchronization solution.
  • Each DSPLL generates any output frequency from any input frequency
  • Support for 1PPS/1Hz input and output frequencies
  • Excellent jitter performance of 100 fs RMS
  • Programmable loop bandwidth per DSPLL as low as 0.001Hz
  • Synchronous, free-run and holdover modes
  • Automatic/manual hitless switching
  • Status monitoring: LOL, LOS, OOF
  • Pin or software controllable DCO on each DSPLL with resolution to 1ppt/step
  • Meets the requirements of:
    • ITU-T G.8262.1 (Enhanced SyncE) eEEC
    • ITU-T G.8273.2 T-BC, T-TSC
    • ITU-T G.8262 (SyncE) EEC Options 1 & 2
    • ITU-T G.8262.1
    • ITU-T G.8261
    • ITU-T G.812 Type III, IV
    • ITU-T G.813 Option 1
    • Telcordia GR-1244, GR-253 (Stratum 3/3E)

Get Started with Si5348/83/84/88/89

Network Synchronization Development Kit

Ramp up your network synchronization development with one of our available development kits.

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Product Matrix

Devices
Part Number Customize Data Sheet Dev Kit Description Control Reference Inputs Clock Outputs Input Frequency min (MHz) Input Frequency max (MHz) Output Frequency min (MHz) Output Frequency max (MHz) Output Format(s) Phase Jitter (RMS) (ps) VDD (V) VDDO (V) Loop Bandwidth Min (Hz) Loop Bandwidth Max (Hz) Package Type Package Size (mm) Clock Generators Jitter Attenuating Clocks Synchronous Ethernet/1588 PCI Express Clocks 4G/LTE Wireless Clocks Intel x86 Clocks
Si5348-E-EVB Network synchronizer and jitter attenuator I2C/SPI 5 7 0.008 750 0.000001 350, 718.5 CML; HCSL; LVCMOS; LVDS; LVPECL 0.125 1.8 + 3.3V 1.8; 2.5; 3.3 0.001 4000 QFN64 9x9 No Yes Yes No No No
Si5383-D-EVB 3-PLL network synchronizer with 1PPS in/out I2C 5 7 0.000001 750 0.000001 350, 718.5 CML; HCSL; LVCMOS; LVDS; LVPECL 0.15 1.8 + 3.3V 1.8; 2.5; 3.3 0.001 4000 LGA56 8x8 No Yes Yes No No No
Si5383-D-EVB 1-PLL network synchronizer with 1PPS in/out I2C 5 7 0.000001 750 0.000001 350, 718.5 CML; HCSL; LVCMOS; LVDS; LVPECL 0.15 1.8 + 3.3V 1.8; 2.5; 3.3 0.001 4000 LGA56 8x8 No Yes Yes No No No
New Si5388
Si5389-EVB 2-PLL Network Synchronizer clock for IEEE 1588v2 SPI 5 8 0.000001 750 0.000001 350, 718.5 CML; HCSL; LVCMOS; LVDS; LVPECL 0.105 1.8 + 3.3 1.8, 3.3 0.001 0.004 LGA64 9x9 No Yes Yes No No No
New Si5389
Si5389-EVB 3-PLL Network Synchronizer clock for IEEE 1588v2 SPI 5 8 0.000001 750 0.000001 350, 718.5 CML; HCSL; LVCMOS; LVDS; LVPECL 0.105 1.8 + 3.3 1.8, 3.3 0.001 0.004 LGA64 9x9 No Yes Yes No No No

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