About This Webinar
TUES., NOV 10TH AT 9:00 CST/16:00 CET
WEDS, NOV 11TH AT 10:30 HKT
Field Programmable Gate Array (FPGA) and application-specific processors/SoC usages are becoming increasingly common in numerous high-performance applications such as networking, data centers, automotive, broadcast video, medical and print imaging and industrial controls. As performance of application increases, more reference clocks with high precision are needed for the end applications. Silicon Labs broad portfolio of flexible, any-frequency clock generators utilize the patented MultiSynth™ technology to provide the most integrated timing solutions without compromising performance. Designing a reference clock tree for a high-performance FPGA or processor/SoC design is an exacting task and at Silicon Labs, we have a clock for that.
45 Minute Presentation
15 Minute Q&A
Senior Product Manager
Linda Lua is the Silicon Labs product manager responsible for managing datacenter timing products and strategy, new products definition and business development. Prior to joining Silicon Labs, Linda was at ISSI, Inc., responsible for high speed memory products, and before that at IDT Inc., responsible for timing products business development and product management in networking and the communications market. Linda holds a BS in Electrical Engineering from Iowa State University and MBA from the University of Texas at Dallas.
Staff Product Manager
Murali Chandran is the Silicon Labs product manager responsible for managing high performance jitter attenuator timing products and strategy, new products definition and business development. Prior to joining Silicon Labs, Murali was at Maxim Integrated responsible for the Portable power products and has done roles in product management, product definition and business development. Murali holds a BS and MS in Electrical Engineering from Texas Tech University and an MBA from the University of Chicago Booth school of business.