About This Webinar
TUES., NOV 17TH AT 9:00 CST/16:00 CET
WEDS, NOV 18TH AT 10:30 HKT
As PCIe data rates increase, the jitter budget for PCIe systems is getting increasingly stringent. Jitter measurements for newer PCIe specifications has an added complexity from noise from measurement equipment, resulting in inaccurate jitter measurements. In this presentation, you will learn about the latest PCIe standard specification and differences between different specifications, how to make accurate PCIe jitter measurements and
Silicon Labs timing solutions to support PCIe Gen 4/5/6.
45 Minute Presentation
15 Minute Q&A
Director of Design Engineering
Greg Richmond is Director of Engineering for the Timing division. He possesses 30 plus years of design experience has been issued 20 patents. Greg is a member of OIF-CEI, PCI-SIG plus various IEEE standards committees. He holds an MSEE from Stanford University and BSEE from Walla Walla University.
Daniel de Godoy
Customer Applications Engineer
Daniel holds an B.Eng./MS/PhD in EE from the Federal University of Pernambuco, Brazil and Columbia University in New York, respectively. He is a also a recipient of the Columbia EE Department Research Award, Science Without Borders Fellowship, and Lemann Foundation Fellowship.
Senior Product Manager
Linda Lua is the Silicon Labs product manager responsible for managing datacenter timing products and strategy, new products definition and business development. Linda holds a BSEE from Iowa State University and MBA from the University of Texas at Dallas.