About This Webinar
TUES., OCT 27TH AT 9:00 CST/16:00 CET
WEDS, OCT 28TH AT 10:30 HKT
Designing a clock tree can be an exacting task. Let Silicon
Labs tools reduce design complexity. In this webinar, you will learn about how
Silicon Labs software tools can help you quickly and easily design an optimal
clock tree, complete with design rule checks to reduce time to market for your
product.
Duration
45 Minute Presentation
15 Minute Q&A
Speakers
Daniel de Godoy
Customer Applications Engineer
Silicon Labs
Daniel de Godoy is currently a customer application engineer in the Timing division. Daniel holds an B.Eng./MS/PhD in EE from the Federal University of Pernambuco, Brazil and Columbia University in New York, respectively. He is a also a recipient of the Columbia EE Department Research Award, Science Without Borders Fellowship, and Lemann Foundation Fellowship.
Tim Paluck
Customer Applications Engineer
Silicon Labs
Tim Paluck is a customer applications engineer for
datacenter timing products, primarily supporting clock generators and oscillators. Tim holds a BS in Electrical Engineering and a MS in Computer Engineering from Southern Methodist University in Dallas.