Automobiles are quickly adopting new sensors, Advanced Driver Assistance Systems (ADAS), automated driving functions, 5G telematics, Ethernet and audio/visual displays to enhance the in-cabin experience and improve passenger and vehicle safety. To enable all of these features and capabilities, systems designs are adopting higher speed processors and GPUs, high bandwidth FPGAs, customized ASICs with high speed SerDes, PCIe Gen3/4/5 and NVLink data buses, and high bandwidth Ethernet switch SoCs. As these devices and data buses are adopted, the associated timing requirements on those designs also become much more complex and require low jitter, single-ended and differential reference clocks. The most common source for reference clocks in the automotive market has been quartz crystals and oscillators, however the increased usage of quartz elements becomes costly, requires additional PCB area, adds points of failure and reduces overall system reliability. To overcome these challenges, Silicon Labs has introduced an entire family of automotive grade, AEC-Q100 qualified clock generators, PCI-Express (PCIe) clocks, PCIe buffers and fanout buffers.
Functional safety, design robustness, and redundancy have become pivotal design requirements in automotive networking, advanced driver assistance systems (ADAS), automated driving, and IVI/digital cockpit electronic designs. The SmartClock features wtihin Si5332-AM address the growing need for health monitoring and fault detection of input reference clocks. Smartclock features can detect if fault condition has occurred, and communicate that to an external system microcontroller or system safety manager. The microcontroller or system safety manager can then instruct the Si5332-AM to migrate from the faulted input source to a backup, redundant reference source to ensure that output clocks continue to be supplied to system endpoints.
Quartz crystals and oscillators are highly susceptible to shock and vibration failure, and therefore deemed high points of failure in an automotive system design. Consolidating the functionality of quartz crystals and oscillators into a silicon-based clock generator greatly reduces the number of points of failure, decreases FIT/DPPM and increases the overall reliability of the design, while at the same time providing additional benefits of frequency flexibility, integrated termination, signal integrity tuning and in-system programmability.
Users can create customized configuration files for both clock generators and fanout buffers, exactly matching system clock requirements in just minutes using the ClockBuilder Pro software utility. The device features up to 7 user-definable hardware input pins that can be assigned to multiple different functions, including output enable for one or more outputs, loss of signal (LOS), frequency control, spread spectrum enablement, or input reference frequency selection. On the clock buffers, the input(s) and outputs can be individually programmed to user-defined format and voltage levels, eliminating the need for external translation resistor and capacitor networks. On the clock generators, the multi-profile feature provides the ability to store up to 16 unique configuration files in the same orderable part number, using the hardware input pins to select between each configuration. When a configuration file is complete, a part number can be generated instantly, with samples available in less than 2 weeks.