EFM32™ PG22 32-bit Microcontrollers (MCUs)

The EFM32PG22 32-bit microcontroller (MCU) family is a pin and software compatible MCU-only version of the award-winning EFR32xG22 wireless SoC platform (BG22, MG22 and FG22). PG22 32-bit MCUs are ideal for enabling a wide range of ultra-low-power and high-performance embedded IoT applications.

The highly efficient PG22 offers a 76.8 MHz Cortex-M33 with rich analog and communication peripherals providing a compact, highly integrated MCU for consumer and industrial markets.

Sleep current with 8k RAM
1.1 μA
Active current as low as
27 μA/MHz

EFM32PG22 Common Specs

  • ARM Cortex-M33
  • 76.8 MHz
  • Up to 512 kB of flash
  • 32 kB RAM
  • 27 μA/MHz Active
  • 1.1 μA EM2 with 8 kB RAM
  • 0.5 uA w/ RTC in EM4
  • 2x USART, 2x I²C, 1x EUART and PDM
  • 16-bit ADC (16 channels)
  • Built-in 32 kHz, 500 ppm sleep XTAL
  • ±2 °C temperature sensor
  • -40 °C to +125 °C
  • 1.71 V to 3.8 V single power supply
  • Packages:
    • 32-pin QFN (4 mm x 4 mm) (18 GPIO)
    • 40-pin QFN (5 mm x 5 mm) (26 GPIO)

Securing Your Product

IoT security is key to protecting company brands, end user privacy and commercial viability of products. Vulnerabilities can be exploited through both remote Internet attacks and physical hands-on-attacks.

Developers using the Silicon Labs wireless product portfolio including those in the EFR32PG22 portfolio have access to a number of technologies designed to protect their product, including Secure Debug, Secure Boot with Root of Trust & Secure Loader.

PG22 Security Features

  • Secure Boot with Root of Trust and Secure Loader (RTSL)
  • Hardware Cryptographic Acceleration for AES128/256, SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA,and ECDH
  • True Random Number Generator (TRNG) compliant with NIST SP800-90 and AIS-31
  • ARM® TrustZone®
  • Secure Debug with lock/unlock
Status
Find the Right EFM32PG22 Device Select Columns
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Part Number MHz Flash RAM Dig I/O Pins Security ADC 1 USB Temp Sensor UART RTC Package Type Package Size (mm) Internal Osc. Debug Interface Cryptography
76 128 32 18 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN32 4 x 4 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 128 32 26 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN40 5 x 5 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 256 32 18 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN32 4 x 4 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 256 32 18 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN40 5 x 5 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 512 32 18 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN32 4 x 4 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 512 32 26 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN40 5 x 5 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 64 32 18 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN32 4 x 4 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2
76 64 32 26 Secure Boot with RTSL 12-bit, 12-ch., 1 Msps 3 QFN40 5 x 5 2% Secure; SW; ETM AES-1 AES-256 ECC SHA-1 SHA-2

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